EMMA HS3 Advanced Hardware OutlineWeek #8
Desktop Motherboards – Chipsets
Top Brands
Intel , Asus, MSI, Gigabyte, Biostar, ASRock, ECS
CPU Socket Type
AMD - 754, 939, 940, AM2, AM2+, AM3, AM3+, FM1, FM2
Intel - 478, 604, 771, 775, 1155, 1156, 1366, 2011
CPU Type
AMD-Sempron, Athlon 64, Athlon 64 X2, Athlon II X2, X3, X4, FX, Phenom
Intel-Pentium 4,Celeron D, Core 2 Duo, Core 2 Quad, Core i3, i5, i7, Extreme
FSB
400 MHz, 533, 667, 800, 1066, 1333, 1600, 2000,QPI 6.4GT/S
Chipsets
Northbridge
Southbridge
Manufacturer’s Product Page via Newegg.com
Newegg Motherboard Specifications
Handouts – Front Side Bus
NorthBridge
SouthBridge
Motherboard Block Diagram
Homework Online -Motherboard Chipsets Quiz
Diagram of a modern motherboard, which supports many on-board peripheral functions as well as several expansion slots
Front Side Bus - From Wikipedia, the free encyclopedia
In personal computers, the front-side bus (FSB) is the bus that carries data between the CPU and the northbridge.
Depending on the processor used, some computers may also have a back-side bus that connects the CPU to the cache. This bus and the cache connected to it are faster than accessing the system memory (or RAM) via the front-side bus.
The bandwidth or maximum theoretical throughput of the front-side bus is determined by the product of the width of its data path, its clock frequency (cycles per second) and the number of data transfers it performs per clock cycle. For example, a 64-bit (8-byte) wide FSB operating at a frequency of 100 MHz that performs 4 transfers per cycle has a bandwidth of 3200 megabytes per second (MB/s):
8B x 100MHz x 4/cycle
= 8B x 100M x Hz x 4/cycle
= 8B x 100M x cycle/s x 4/cycle
= 3200MB/s
The number of transfers per clock cycle is dependent on the technology used. For example, GTL+ performs 1 transfer/cycle, EV6 2 transfers/cycle, and AGTL+ 4 transfers/cycle. Intel calls the technique of four transfers per cycle Quad Pumping.
Many manufacturers publish the speed of the FSB in MHz, but often do not use the actual physical clock frequency but the theoretical effective data rate (which is commonly called megatransfers per second or MT/s). This is because the actual speed is determined by how many transfers can be performed by each clock cycle as well as by the clock frequency. For example, if a motherboard (or processor) has a FSB clocked at 200 MHz and performs 4 transfers per clock cycle, the FSB is rated at 800 MT/s.
History and current usage
The front-side bus is an alternative name for the data and address buses of the CPU as defined by the manufacturer's datasheet. The term is mostly associated with the various CPU buses used on PC-related motherboards (including servers etc), seldom with the data and address buses used in embedded systems and similar small computers.
Front-side buses serve as a connection between the CPU and the rest of the hardware via a chipset. This chipset is usually divided in a northbridge and a southbridge part,and is the connection point for all other buses in the system. Buses like the PCI, AGP, and memory buses all connect to the chipset in order for data to flow between the connected devices. These secondary system buses usually run at speeds derived from the front-side bus clock, but are not necessarily synchronous to it.
Related component speeds
CPU
The frequency at which a processor (CPU) operates is determined by applying a clock multiplier to the front-side bus (FSB) speed in some cases. For example, a processor running at 3200 MHz might be using a 400 MHz FSB. This means there is an internal clock multiplier setting (also called bus/core ratio) of 8. That is, the CPU is set to run at 8 times the frequency of the front-side bus: 400 MHz × 8 = 3200 MHz. By varying either the FSB or the multiplier, different CPU speeds can be achieved.
Memory
Setting an FSB speed is related directly to the speed grade of memory a system must use. The memory bus connects the northbridge and RAM, just as the front-side bus connects the CPU and northbridge. Often, these two buses must operate at the same frequency. Increasing the front-side bus to 450 MHz in most cases also means running the memory at 450 MHz.
In newer systems, it is possible to see memory ratios of "4:5" and the like. The memory will run 5/4 times as fast as the FSB in this situation, meaning a 400 MHz bus can run with the memory at 500 MHz. This is often referred to as an 'asynchronous' system. It is important to realize that due to differences in CPU and system architecture, overall system performance can vary in unexpected ways with different FSB-to-memory ratios.
In image, audio, video, gaming, FPGA synthesis and scientific applications that perform a small amount of work on each element of a large data set, FSB speed becomes a major performance issue. A slow FSB will cause the CPU to spend significant amounts of time waiting for data to arrive from system memory. However, if the computations involving each element are more complex, the processor will spend longer performing these; therefore, the FSB will be able to keep pace because the rate at which the memory is accessed is reduced.
Peripheral buses
Similar to the memory bus, the PCI and AGP buses can also be run asynchronously from the front-side bus. In older systems, these buses are operated at a set fraction of the front-side bus frequency. This fraction was set by the BIOS. In newer systems, the PCI, AGP, and PCI Express peripheral buses often receive their own clock signals, which eliminates their dependence on the front-side bus for timing.
Overclocking
Overclocking is the practice of making computer components operate beyond their stock performance levels.
Many motherboards allow the user to manually set the clock multiplier and FSB settings by changing jumpers or BIOS settings. Almost all CPU manufacturers now "lock" a preset multiplier setting into the chip. It is possible to unlock some locked CPUs; for instance, some Athlons can be unlocked by connecting electrical contacts across points on the CPU's surface. For all processors, increasing the FSB speed can be done to boost processing speed by reducing latency between CPU and the northbridge.
This practice pushes components beyond their specifications and may cause erratic behavior, overheating or premature failure. Even if the computer appears to run normally, problems may appear under a heavy load. Most PCs purchased from retailers or manufacturers, such as Hewlett-Packard or Dell, do not allow the user to change the multiplier or FSB settings due to the probability of erratic behavior or failure. Motherboards purchased separately to build a custom machine are more likely to allow the user to edit the multiplier and FSB settings in the PC's BIOS.
Pros and Cons
Pros
Although the front-side bus architecture is an aging technology, it does have the advantage of high flexibility and low cost. There is no theoretical limit to the number of CPUs that can be placed on a FSB, though performance will not scale linearly across additional CPUs (due to the architecture's bandwidth bottleneck).
Cons
The front-side bus as it is traditionally known may be disappearing, but it's still being used in all of Intel's Atom, Celeron, Pentium, and Core 2 processor models. Originally, this bus was a central connecting point for all system devices and the CPU. In recent years, this has been breaking down with the increasing use of individual point-to-point connections like AMD's HyperTransport and Intel's QuickPath Interconnect. The front-side bus has been criticized by AMD as being an old and slow technology that bottlenecks today's computer systems. While a faster CPU can execute individual instructions faster, this is wasted if it cannot fetch instructions and data as fast as it can execute them; when this happens, the CPU must wait for one or more clock cycles until the memory returns its value. Furthermore, a fast CPU can be delayed when it must access other devices attached to the FSB. Thus, a slow FSB can become a bottleneck that slows down a fast CPU. FSB's fastest transfer speed is currently 1.6 GT/s, which provides only 80% of the theoretical bandwidth of a 16-bit HyperTransport 3.0 link as implemented on AM3Phenom II CPUs, only half of the bandwidth of a 6.4 GT/s QuickPath Interconnect link, and only 25% of the bandwidth of a 32-bit HyperTransport 3.1 link. In addition, in an FSB-based architecture, the memory must be accessed via the FSB. In HT- and QPI-based systems, the memory is accessed independently by means of a memory controller on the CPU itself, freeing bandwidth on the HyperTransport or QPI link for other uses.
A typical north/southbridge layout
Northbridge
The north bridge, also known as the memory controller hub (MCH) in Intel systems (AMD, VIA, SiS and others usually use 'northbridge'), is traditionally one of the two chips in the core logic chipset on a PC motherboard, the other being the southbridge. Separating the chipset into northbridge and southbridge is common, although there are rare instances where these two chips have been combined onto one die when design complexity and fabrication processes permit it.
Overview
The northbridge typically handles communications among the CPU, RAM, BIOS ROM, and PCI Express (or AGP) video cards, and the southbridge.[1][2] Some northbridges also contain integrated video controllers, also known as a Graphics and Memory Controller Hub (GMCH) in Intel systems. Because different processors and RAM require different signaling, a northbridge will typically work with only one or two classes of CPUs and generally only one type of RAM.
There are a few chipsets that support two types of RAM (generally these are available when there is a shift to a new standard). For example, the northbridge from the NvidianForce2 chipset will only work with Socket A processors combined with DDR SDRAM, the Intel i875 chipset will only work with systems using Pentium 4 processors or Celeron processors that have a clock speed greater than 1.3 GHz and utilize DDR SDRAM, and the Intel i915g chipset only works with the Intel Pentium 4 and the Celeron, but it can use DDR or DDR2 memory.
Etymology
The name is derived from drawing the architecture in the fashion of a map. The CPU would be at the top of the map comparable to due north on most general purpose geographical maps. The CPU would be connected to the chipset via a fast bridge (the northbridge) located north of other system devices as drawn. The northbridge would then be connected to the rest of the chipset via a slow bridge (the southbridge) located south of other system devices as drawn.
Recent developments
The memory controller, which handles communication between the CPU and RAM, has been moved onto the processor die by AMD in AMD64 processors and by Intel with their Nehalem processors. Advantages of having the memory controller integrated on the CPU die is reduced latency from the CPU-to-Memory so the CPU can control the memory directly.
Another example of this kind of change is Nvidia's nForce3 chipset for AMD64 systems that is a single chip. It combines all of the features of a normal southbridge with an AGP port and connects directly to the CPU. On nForce4 boards they consider this to be an MCP (Media Communications Processor).
North bridge and overclocking
The northbridge plays an important part in how far a computer can be overclocked, as its frequency is used as a baseline for the CPU to establish its own operating frequency. This chip's temperature typically increases as processor speed becomes faster, requiring increased cooling measures. There is a limit to CPUoverclocking, as digital circuits are limited by physical factors such as propagation delay which increases with (among other factors) operating temperature, therefore most overclocking applications have software limitations which limit the multiplier and external clock setting.
Southbridge
The southbridge, also known as an I/O controller hub (ICH) in Intel systems (AMD, VIA, SiS and others usually use 'southbridge'), is a chip that implements the "slower" capabilities of the motherboard in a northbridge/southbridge chipset computer architecture.
The southbridge can usually be distinguished from the northbridge by not being directly connected to the CPU. Rather, the northbridge ties the southbridge to the CPU. Through the use of controller integrated channel circuitry, the northbridge can directly link signals from the I/O units to the CPU for data control and access.
Overview
Because the southbridge is further removed from the CPU, it is given responsibility for the slower devices on a typical microcomputer. A southbridge usually works with several different northbridges, but these two kinds of chip must be designed to work together; there is no industry-wide standard for interoperability between different core logic chipset designs. Traditionally the interface between a northbridge and southbridge was simply the PCI bus, but because this created a performance bottleneck, most current chipsets use a different (often proprietary) interface with higher performance.
Etymology
The name is derived from drawing the architecture in the fashion of a map and was first described as such with the introduction of the PCI Local Bus Architecture in 1991. At Intel, the authors of the PCI specification viewed the PCI local bus as being at the very center of the PC platform architecture (i.e., at the Equator).
The northbridge extends to the north of the PCI bus backbone in support of CPU, Memory/Cache, and other performance-critical capabilities. Likewise the southbridge extends to the south of the PCI bus backbone and bridges to less performance-critical I/O capabilities such as the disk interface, audio, etc.
The PCI unit is located at the top of the map at due north. The CPU is connected to the chipset via a fast bridge (the northbridge) located north of other system devices as drawn. The northbridge is connected to the rest of the chipset via a slow bridge (the southbridge) located south of other system devices as drawn.
Although the current PC platform architecture has replaced the PCI bus backbone with faster I/O backbones, the bridge naming convention remains.
Functionality
The functionality found in a contemporary southbridge includes:
- PCI bus. The PCI bus support includes the traditional PCI specification, but may also include support for PCI-X and PCI Express.
- ISA bus or LPC Bridge. Though the ISA support is rarely utilized, it has interestingly managed to remain an integrated part of the modern southbridge. The LPC Bridge provides a data and control path to the Super I/O (the normal attachment for the keyboard, mouse, parallel port, serial port, IR port, and floppy controller) and FWH (firmware hub which provides access to BIOSflash storage).
- SPI bus. The SPI bus is a simple serial bus mostly used for firmware (e.g., BIOS) flash storage access.
- SMBus. The SMBus is used to communicate with other devices on the motherboard (e.g., system temperature sensors, fan controllers).
- DMA controller. The DMA controller allows ISA or LPC devices direct access to main memory without needing help from the CPU.
- Interrupt controllers such as 8259A and/or I/O APIC. The interrupt controller provides a mechanism for attached devices to get attention from the CPU.
- Mass storage controllers such as PATA and/or SATA. This typically allows direct attachment of system hard drives.
- Real-time clock. The real time clock provides a persistent time account.
- Power management (APM and ACPI). The APM or ACPI functions provide methods and signaling to allow the computer to sleep or shut down to save power.
- Nonvolatile BIOS memory. The system CMOS, assisted by battery supplemental power, creates a limited non-volatile storage area for system configuration data.
- AC'97 or Intel High Definition Audio sound interface.
- Out-of-band management controller such as a BMC or HECI.
Optionally, a southbridge also includes support for Ethernet, RAID, USB, audio codec, and FireWire. Rarely, a southbridge may also include support for the keyboard, mouse, and serial ports, but normally these devices are attached through another device referred to as the Super I/O.