Reducing the Bond Frame Width in Cu/Sn SLID Wafer Level Packaging

Ani Duan, Guttorm.Salomonsen, Kaiying Wang, Knut Aasmundtveit and Nils Hoivik

IMST-Department of Micro and Nano Systems Technology, HiVe-Vestfold University College

Postbox 2243, N-3103 Tønsberg, Norway. Tel. 0047-33037941

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ABSTRACT

Cu/Sn SLID bonding technique is a promising candidate for MEMS packaging due to high temperature stability and low cost. As of today, research on Cu/Sn bonding has mainly focused on interconnects, while a few articles have explored the technology for wafer-level packaging [1-3]. However, reducing the overall size of the package has not yet been emphasized for Cu/Sn bonding, which is important to account for, since the package size may be significantly larger than the functional device itself [4]. Therefore investigation on reducing the overall size of the package is important for MEMS development. In this paper, we investigated the minimum practical width of Cu/Sn bond frames for wafer level packaging. The effect of bond frame width on bonded result has been reported.

In previous work, the Cu/Sn bond frame width is 200 mm, and was found to sufficiently provide a sealed package [1]. In a similar process, but using Au/Sn, 80 mm wide bond frames were used for hermetic bonding [5]. In order to verify a suitable width range in Cu/Sn wafer level packaging, the width of the bond frame is designed from 200 to 80 mm. Figure 1 presents a schematic illustration of one Cu/Sn sealed package chip (left top) and reference chip (left bottom). Exposed to atmospheric pressure after vacuum bonding, the membrane on the cap wafers of the successfully bonded chips deflect towards the substrate wafers. Sealing yield is defined as the percentage of membranes showing deflection.

A typical photograph of wafer after dicing (middle of figure 2) and interferometer measurements of cap wafer deflection is shown in figure 2. Compared to the flat surface of reference chip (left side of figure 2), the deformed surface of package chip (right side of figure 2) indicates that the package chip is sealed. Preliminary results show that 100% dicing yield is obtained after dicing the bonded wafers with 200, 150, 110 mm bond frame widths. Here the dicing yield is defined as the percentage of not stripped package chips during the dicing process. The 80 mm bond fame width is lacks because of the not finished processing. And it will include in the final paper. The sealing yield of these bonds is plotted in figure 3, where the yield decreases with the decreasing bond frame width. It might be associated with the bond frame delamination. Figure 4 shows a cross section microscopy image of an optimized bond frame, showing a symmetric Cu / Cu3Sn / Cu sandwich structure.

The preliminary work demonstrates wafer level Cu/Sn SLID bonding technique with bond frame width from 200 mm to 110 mm. The optimized bond frame width is around 110 mm for providing a high mechanical and hermetical property for the package. The experiment result of 80 mm bond frame width will be presented in the final paper.

Keywords: Wafer level bonding, Cu/Sn SLID, and MEMS technology.

REFERENCE

[1] C. Yuhan and L. Le, "Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology," Journal of semiconductors, vol. 30, 2009.

[2] A. Lapadatu, et al., "Cu-Sn Wafer Level Bonding for Vacuum Encapsulation of Microbolometers Focal Plane Arrays," presented at the ECS Transactions, 2010.

[3] N. Hoivik, et al., "Fluxless wafer-level Cu-Sn bonding for micro- and nanosystems packaging," presented at the ESTC 2010, Berlin, 2010.

[4] J. Jozwiak, et al., "Integrating Through-Wafer Interconnects With Active Devices and Circuits," IEEE Transactions on advanced packaging, vol. 31, pp. 4-13, 2008.

[5] F. Theunis, et al., "A novel and efficient packaging technology for RF-MEMS devices," in 2007 electronic components and technology conference, 2007, pp. 1239-1245.

Figure 1: Schematic illustration of test structure used to determine if there is vacuum inside the package after bonding. Cross-section (left) and top view (right). Note, not to scale.

Figure 2: Experimental result with 110 mm wide bond frames. Photograph of the wafer shows 100% dicing yield (middle), while interferometer scans of a reference chip (left) without a cavity and one of the sealed packages (right).

Figure 3: The sealing yield for each bond frame width. 80 mm width of bond frame is currently under investigation. / Figure 4: Cross-section of 110 mm bond frame. The bonding force was 7 kN at 270 oC for 30 minutes. The bond line consists of Cu/Cu3Sn/Cu as confirmed by EDX.