EEN1036: Digital Logic Design, Lab Exp. DL2

______

EEN1036: DIGITAL LOGIC DESIGN

EXPERIMENT 2: Flip-flops and Their Applications

Objective

The objective of this experiment is to introduce students to flip-flops and their applications.

Note: There are three parts in this experiment. They are:

  1. JK flip-flop
  2. Ripple binary counter using JK Flip-flop
  3. Synchronous binary counter using JK Flip-flop

You are required to complete all of them.

Preparation

Before starting the experiment, make sure that you have the following equipment and components.

Equipment

  1. DC power supply - 1
  2. Function Generator -1
  3. Oscilloscope - 1

Components

  1. Breadboard - 1
  2. IC 7408 (quad AND gate) - 1
  3. IC 7473 (dual J-K flip-flop) - 2
  4. Resistor 1.2K - 3
  5. Resistor 4.7K - 3
  6. LED - 3
  7. Function generator probe - 1

Experiment 2A: Design of JK Flip-flop (30 minutes)

The next outputs of a sequential circuit depend on its inputs as well as its present state. It has a storage capacity. Flip-flops are the basic building blocks of sequential circuits. Common flip-flop types are S-R, D, JK and T. The JK flip-flop is regarded as the most versatile one. Normally, it functions as S-R flip-flop (J refers to set, K refers to reset). It can be used to design both D and T flip-flops. The characteristic table of the JK flip-flop is given in Table 2.1.

Table 2.1 JK flip-flop characteristic table

Clock / J K / Present state / Next state / Mode of operation
0 / x x / Q0 / Q0 / hold
↓
↓
↓
↓ / 0 0
0 1
1 0
1 1 / Q0
Q0
Q0
Q0 / Q0
0
1
Q0’ / hold
reset
set
toggle


Fig 2.1 JK flip-flop

Experimental Procedures

This part of the experiment will examine the functional behavior of JK flip-flop. The experiment setup is shown in Fig 2.2.

Fig 2.2 JK flip-flop test setup

By now you should be familiar with digital logic experiment procedures. The following description will be brief.

Getting ready the power supply: Set the output voltage to +5V. Set the ammeter scale switch to LO (if any). Set the current adjustment knob to about ¼ turn from the min position. Connect the “-“ output terminal to the “GND” terminal. Ask your supervisor if you have any query.
  1. Make sure that the power supply is turned off. Connect two jumper wires from the DC power supply's +5V and GND (ground) points to two horizontally connected lines on your breadboard, respectively.
  2. Insert one 7473 IC on the breadboard.Note that you will use up to 3 ICs in exp. 2B.2. Distribute your ICs on your breadboard.
  3. Please make sure that the IC and other components are placed firmly on the breadboard, otherwise, get a new breadboard from the lab.
  4. Connect pin 4 of 7473 IC to +5V.
  5. Connect pin 11 of 7473 IC to GND.
  6. Complete the circuit connections as shown in Fig 2.2. Use jumper wires as switches, including the reset switch.

  1. Getting ready the function generator: Set the function generator to squared pulse generation mode. Select the 10 Hz frequency range button (1 second counter gate time). Set the function generator's frequency to about 2 Hz.

  1. Make sure that the function generator is turned off. Connect the function generator probe to the function generator’s SYNC OUT located at the rear panel (this output is TTL compatible).
  2. Connect the positive line of the probe to pin 1 of IC 7473.
  3. Connect the ground lead (long end) of the probe to the common ground point.

  1. Getting ready the oscilloscope: Set time base scale to 0.5 ms/div and vertical scales to 5 V/div. Make sure that the VARIABLE of the TIME DIV is at the CAL position. Do not turn off the oscilloscope (warming up is required).

  1. Connect the clock input and the flip-flop output to oscilloscope channel 1 (CH1) and channel 2 (CH2) respectively, as indicated in Fig 2.2.
  2. Verify your connections again.
  3. Now you are ready for the experiment. Turn on the DC power supply.
  4. Turn on the function generator.

Observation

  1. Complete Table R2.1 in that sequence. Repeat this experiment to confirm your results.
  2. Keep S1 and S2 in the OPEN (1) state. Increase the clock frequency to 1KHz. Record the waveform of the flip-flop output Q (CH2) with respect to the clock waveform in Fig R2.1.
  3. Hold the reset button in closed (0) position. Observe the change of the waveform of the flip-flop output Q (CH2). Record your observation in experimental result section.

[1 mark]

This is the end of this part of the experiment.

Switch off the power supply, the function generator and the oscilloscope.

Note that the circuit in Fig 2.2 will be used in the next experiment with some modifications.

Experiment 2B: Application of Flip-Flop –Design of Binary Counter

A binary counter is a kind of sequential circuit. It counts the input pulses appearing at its input. Counters can be designed in many different ways. Two basic types that will be covered in this experiment are:

  1. Ripple binary counter and
  2. Synchronous binary counter

2B.1: Design of Ripple Binary Counter using JK Flip-flop (45 minutes)

In a ripple or asynchronous counter, the change of state of each stage occurs after the state change in its previous stage. Such counters are easy to design. Its main disadvantage is that it is a slow counter. Toggle (T) flip-flops are used to design the counter circuit. T flip-flops can be easily designed using JK flip-flops by tying its JK inputs together to VCC. Fig 2.3 shows a T flip-flop constructed from a JK flip-flop.

Fig 2.3 (a) Toggle flip-flop and (b) output waveform

Your experiment will be to construct a 3-bit ripple binary counter. 3-bit counter requires 3 T flip-flops. IC 7473 contains 2 JK flip-flops. Therefore, you need two 7473 ICs. The circuit for the experiment is shown in Fig 2.4.

Fig 2.4 3-bit ripple binary counter

Experimental Procedures

Note that ONLY TWO 7473 ICs are used in this experiment.

  1. Make sure that the power supply and the function generator are turned off.
  2. Insert another 7473 ICs on the breadboard. Note that you will use up to 3 ICs ONLY in exp. 2B.2. Distribute your ICs on your breadboard.
  3. Please make sure that the IC and other components are placed firmly on the breadboard, otherwise, get a new breadboard from the lab.
  4. Connect pin 4 and pin 11 of this IC to +5V and GND, respectively.
  5. Complete the circuit connections as shown in Fig 2.4.
  6. Set the function generator's frequency to 2 Hz (refer to procedure 6 and 7 in exp. 2A if necessary). You may need to reduce the frequency to 1 Hz if you cannot record your results in the observation part.
  7. Verify your connections again.
  8. Now you are ready for the experiment. Turn on the DC power supply.
  9. Push the reset button to reset all the flip-flops. It will turn off all the LEDs.
  10. Turn on the function generator.

Observation

Complete Table R2.2 in that sequence. Repeat this experiment to confirm your results.

[2 marks]

This is the end of this part of the experiment.

Switch off the power supply and the function generator.

Note that the circuit in Fig 2.4 will be used in the next experiment with some modifications.

2B.2: Design of Synchronous Binary Counter using JK Flip-flop (1 hour)

A synchronous binary counter's states change synchronously with the clock edge. This counter is faster than ripple binary counters. All the flip-flops in a synchronous binary counter share a common clock. A 3-bit synchronous binary counter circuit is shown in Fig 2.5.

Fig 2.5 3-bit synchronous binary counter

Experimental Procedures

  1. Make sure that the power supply and the function generator are turned off.
  2. Insert one 7408 IC on the breadboard and connect pin 14 to +5V and pin 7 to GND.
  3. Complete the circuit connections as shown in Fig 2.5.
  4. Verify your connections again.
  5. Now you are ready for the experiment. Turn on the DC power supply unit.
  6. Push the reset button to reset all the flip-flops. It will turn off all the LEDs.
  7. Turn on the function generator.

Observation

Complete Table R2.3 in that sequence. Repeat this experiment to confirm your results.

[2 marks]

At the end of this experiment: switch off all the equipment, open all the connections and return all the components used.

Summary

In this experiment, you have learned how to design, analyze and evaluate a binary counter.

APPENDIX

Page 1 of 10

EEN1036: Digital Logic Design, Lab Exp. DL2 result and mark sheets

Student ID ……………………… Name ………………………………….. Major ………………………….

EXPERIMENTAL RESULTS AND DISCUSSIONS

Exp. 2A: JK flip-flopAnalysis

  1. Table R2.1: Observation results of J-K flip-flop

Operational sequence / S1 / S2 / LED (ON/OFF) / Mode of operation
0 (Push the reset button) / CLS (0) / CLS (0) / OFF
1 (Release the reset button) / CLS (0) / CLS (0)
2 / OPEN (1) / CLS (0)
3 / CLS (0) / CLS (0)
4 / CLS (0) / OPEN (1)
5 / CLS (0) / CLS (0)
6 / OPEN (1) / OPEN (1)
  1. Fig R2.1: Measured waveforms of clock and J-K flip-flop output Q

Clock

J-K flip-flop output Q

  1. When the reset button is held in closed position, what is the output Q of the J-K flip-flop? ______
  1. From the measured waveforms in Fig R2.1

i)When the flip-flop output starts to change state? The positive or negative edge of the clock? ______

ii)What is the frequency of the flip-flop output? ______

Exp. 2B.1: Ripple binary counter Analysis and Evaluation

  1. Table R2.2: Observation results of the ripple binary counter

(Use binary 0 to represent LED OFF and binary 1 to represent LEDON)

Sequence No./
Clock Pulse No. / MSB
Q2 / Q1 / LSB
Q0 / Decimal
0 (Push the reset button) / 0 / 0 / 0 / 0
1 (Release the reset button)
2
3
4
5
6
7
8
9
10
  1. From the experimental results in Table R2.2, draw the waveforms at Q0, Q1 and Q2 in Fig R2.2.

Fig R2.2: Waveforms of clock, Q0, Q1 and Q2 of the ripple binary counter

Pulse No. 012345678910

Clock

Q0

Q1

Q2

Exp. 2B.2: Synchronous Binary CounterAnalysis and Evaluation

  1. Table R2.3: Observation results of the synchronous binary counter

Sequence No./
Clock Pulse No. / MSB
Q2 / Q1 / LSB
Q0 / Decimal
0 (Push the reset button) / 0 / 0 / 0 / 0
1 (Release the reset button)
2
3
4
5
6
7
8
9
10
  1. From the results in Table R2.3 and circuit diagram in Fig 2.5, draw the waveforms at Q0, Q1, Pin 3(7408) and Q2 in Fig R2.3.

Fig R2.3: Waveforms of clock, Q0, Q1, Pin 3(7408) and Q2 of the synchronous binary counter

Pulse No. 012345678910

Clock

Q0

Q1

Pin 3(7408)

Q2

  1. From Fig R2.3 and Fig 2.5, describe the function of the AND gate.
  1. If a clock frequency fclk is applied to an n-bit binary counter, what is the frequency of the final stage flip-flop output (Qn-1)? Show your derivation. Fig R2.2 or R2.3 can help you in this derivation.

Part 1: Experiment 2A
(JK flip-flop)
1 Mark
Part 2: Experiment 2B.1
(Ripple Binary counter using JK flip-flop)
2 Marks
Part 3: Experiment 2B.2
(Synchronous Binary counter using JK flip-flop)
2 Marks
TOTAL (5 Marks)

Page 1 of 10