ECE 4260/5260 Mixed Signal IC Design. Final Exam, Name ______
Answer all the questions.
I.a) Explain with diagram architecture of integrating dual slope A/D converter. What are
The advantage and disadvantage of this converter.
b)What is the worst case conversion time for 16 bit dual slope A/D converter when the clock rate is 10 MHz?
c) If Vref =5V for the above converter, and integrating capacitor is 50pF, for a clock frequency of 1Mhz, what is the resistor value needed so that the opamp output never exceeds 5V when the input voltage is between 0V to 5V.
d) What signal input frequencies are completely attenuated for this converter (converter in part c)?
e) For the converter in part (c) what is the attenuation of signal at 60 Hz?
II. a)What are advantages and disadvantages of oversampling in data converters?
b) Assuming oversampling with noise shaping, find the approximate sampling rate required to obtain a maximum SNR of 60 dB on a signal with 1-KHz bandwidth using a 1 bit quantizer.
c) Find the first five sequence and state values for an input voltage of 0.45 V for a two level quantizer of +1.0 V with threshold at zero, and the initial state x(n)=0.2.
At what frequency relative to sampling rate fs, would a tone appear?
Does the averaging result in input value?
d) What is the advantage of over sampling with noise shaping?
e) Give the architecture of modulator with second order noise shaping.
f) Show that SNRmax = 6.02N + 1.76 -5.17 + 30 log (OSR) for first order noise shaping.
g) Realize this modulator using switched capacitor approach.
III. a) For a successive approximation A/D converter with signed input, the input voltage is 3.15V and the reference voltage Vref=8V. Find the sequence of 4-bit D/A converter’s output levels. What is the final digital output (offset binary code).
b) 1) Give the architecture of a 3 bit flash D/A converter. How do you minimize the bubble error.
2) What are the approaches to minimize the number of comparators required for high resolution flash A/D converter.
3) What is the accuracy of resistors required to design a 6 bit flash A/D?
c)1) Explain the principle and draw the architecture of 5 bit pipelined A/D converter.
2) If Vref= +2.5 V, determine the outputs of the pipelined 5 bit A/D converter for 5 clock pulses. Vin = 1.5V.
IV. a) What are the advantages of switched capacitor circuit and what is its application.
What are the advantages of signal-flow graph analysis for switched capacitor
circuits.
b) Find the discrete-time transfer function of the first order switched capacitor filter using signal-flow graph analysis.
c) Find the capacitance values needed for a first order switched capacitor circuit such that its 3db frequency 1KHz and clock frequency is 50Khz. The filter should have a zero at 25kHz and a DC gain of 2. CA=10pF.
d) We need a resistor of 1M ohm implemented by a switched capacitor of 1 pF. What is the frequency of clock? Show the circuit diagram.