This three-column page will list our major on-line content:

> Chip Design Trends (first column)

> e-Newsletter viewpoints and mini-series (second column)

> iDesign (third column)

> blogs (if space is available)

I. First Column:

@head: Chip Design Trends

Track the trends in pre-silicon chip designs as covered by such experts as Dave Bursky, Geoffrey James, Erach Desai and others. Recent insights include:

·  Industry Leaders Share Their Insights Into Current Design Trends

To deliver top-notch performance and unheralded levels of integration, the next generations of integrated circuits will leverage a combination of deep-submicron lithography and processing tricks. In terms of lithography, perhaps as many as a dozen layers of copper metallization will be used for interconnect. Future processing tricks may include …

·  Analysis Of Design Profile Data For Launch Issue Of Design Trends

We profile the results of more than 34,000 system-on-a-chip (SoC) design investigations. Over the past seven quarters, these design investigations have been extensively and exhaustively analyzed by a variety of design teams. In terms of count, they aren’t actual design starts. But the percentages in our analysis do reflect how new design starts

·  Seasonal Cycles Of Change

Intellectual-property (IP) demand is notoriously difficult to measure. While industry analysts can successfully explain major market trends, it’s next to impossible to get the kind of month-by-month data that would reveal how the IP market actually behaves. Fortunately, examining the browsing behavior of chip designers can provide a valuable

snapshot of IP buying habits …

·  Measure Project Success By Performance, Power, And Area

If you ask any chip designer for the three most important technical parameters to any design, the answer will typically be performance. Such performance is measured as throughput or clock speed, total power consumed by the chip, and total die area. By understanding how designers and project managers balance these three critical parameters to satisfy...

II. Second Column

e-Newsletters

Check out the latest industry viewpoint pieces and news packed into every issue of the e-newsletter. Here’s a sample of this month’s topics:

FPGA Developer

·  Core-assisted Debug

·  Advanced Verification Drives Home Advanced FPGAs

Wireless Chip Designer

·  Class D Amplifiers Empower Mobile Multimedia

·  4D Wireless Broadband Initiative Announced

Chip Designer

·  Structured ASICs Are Alive and Well

·  Automated Design-for-Test Simplifies Flow

e-Newsletter Mini-series:

New mini-series tackles today’s design challenges! Read the first of each three part mini-series in latest issue of these popular e-Newsletters:

I. FPGA Developer

Quality-of-Result (QoR) Mini-series:

> Editor’s Perspective: "The Real Story Behind FPGA-Based Quality-of-Results (QoR)"

> EDA Perspective: “Quality of Results is Everything for FPGA Designs – or is it?”

> Semicon Perspective: “Ease of Design Compliments FPGA Performance Goals”

ASIC Prototyping Mini-series:

> Editor’s Perspective: “ASIC Prototyping with FPGAs -- A Double-Edge Sword!”

> EDA Perspective: “ASIC Prototyping with FPGAs – YES, Please!”

> Semicon Perspective: “ASIC Prototyping with FPGAs”

II. Wireless Chip Designer

Analog-RF SoC Mini-series:

> Editor’s Perspective: “Will analog-RF designs every truly fit in the SoC World?”

> EDA Perspective: “Effects of EDA Evolution on RFIC Design”

> Semicon Perspective: “That 80's Show or AMS IP Creation Flashback”

III. Third Column

iDesign:

@head: Vast Technologies -- “We Must Support Standards …and Deliver Open Development Environments”

@text: Companies delivering embedded system design tools must invest in the development of solutions that address both design and supply chain challenges – when customers win, we win!

@head: Mentor – “Transaction-Level Modeling is Critical for an Effective Functional Verification Methodology”

@text: Complexity drives greater degrees of abstraction, driving the shift in focus from the register transfer level to the transaction level. Consequently, the most successful advanced verification methodology will be one which is based upon transaction-level modeling (TLM).

@head: “The Man With The Twisted IP [TWIS]”

@text: Sherlock Holmes pointed the way. We realized we needed data about that IP, and lots of it. It quickly became apparent that all information required to make rational design decisions didn't exist in one place or one format...

@head: Max's Chips and Dips – “Escape from Analog Alcatraz”

@text: Although incredible useful, analog PCells have (until now) effectively been "restrained behind bars." Enter those little scamps at Ciranova, who have just unlocked the door and thrown away the key!

@head: Max's Chips and Dips: “Prisoner PCell Block A”

My “lack” of knowledge with regard to the analog domain is encyclopedic, so I was enthralled to be regaled with a tale so terrible as to make even the strongest amongst us quiver at the knees.