ESF grant: 3658 (1999-2002)

Title: Digital Electronics Design & Test Virtual Laboratory

Principal investigator:prof. R.Ubar

Abstract: The main goal is to create a virtual internet based electronics design and test laboratory, and to prove its vitality by increasing the efficiency of the R&D work in design and test of digital circuits and systems. Originality and novelty of the project idea is in creating a novel Web-based CAD environment in the form of an international virtual laboratory. Investigations have been carried out for possible solutions to create internet based design environment. Corresponding networking software, web-server extensions and user-tools interfaces have been developed. By using this environment cooperative experimental researh has been carried out. New results have been obtained in high-level test generation by increasing the efficiency of algorithms [1], and by implementing the ideas of concurrency [6] and genetics [7]. A new method in cooperation with TIMA Grenoble for design error diagnosis in digital circuits that doesn’t use any error model was developed [2-4]. For representing the information about erroneous signal paths in the circuit, stuck-at fault model is used. This allows to adopt the methods and tools of fault diagnosis used in hardware testing for using in design error diagnosis. Contrary to other published works, the necessary re-synthesis of the extracted subcircuit need not be applied to the whole function of an internal signal in terms of primary inputs, but may stop at arbitrary nodes inside the circuit. As the subcircuits to be redesigned are kept as small as possible, the redesign procedure is simple and fast. A new class of DD representation, called Register-Oriented DDs (RODD) has been introduced [5]. The model appeared to be an efficient and compact representation of the system behavior for high-level cycle simulation. In order to fully exploit the advantages of RODDs, new simulation algorithms which are a combination of cycle-based forward event-driven and recursive back-tracing techniques were proposed. The higher speed of simulation in comparison with commercial tools was shown by cooperative experiments with researchers from Fourier’ University in Grenoble.

Publications:

  1. J.Raik, R.Ubar. High-Level Path Activation Technique to Speed Up Sequential Circuit Test Generation. Proc. of IEEE European Test Workshop, Constance, May 25-28, 1999, pp.84-89.
  2. R.Ubar, D.Borrione. Design Error Diagnosis in Digital Circuits without Error Model. 10th IFIP Int. Conf. on VLSI’99. Lisboa, Dec. 1-4, 1999, pp.281-292.
  3. R.Ubar, A.Jutman. Hierarchical Design Error Diagnosis in Combinational Circuits by Stuck-at Fault Test Patterns. Proc. of the 6th International Conference on Mixed Design of Integrated Circuits and Systems. Krakow (Poland), June 17-19, 1999, pp. 437-442.
  4. A.Jutman, R.Ubar. Design Error Diagnosis in Digital Circuits with Stuck-at Fault Model. Journal of Microelectronics Reliability. Pergamon Press, Vol. 40, No 2, 2000, pp.307-320.
  5. R.Ubar, A.Morawiec, J.Raik. Back-Tracing and Event-Driven Techniques in High-Level Simulation with Decision Diagrams. Proc. of the IEEE ISCAS’2000 Conference, Geneva, May 28-31, 2000, Vol. 1, pp. 208-211.
  6. R.Ubar, M.Brik.Hierarchical Concurrent Test Generation for Synchronous Sequential Circuits. Proc. of the 7th International Conference on Mixed Design of Integrated Circuits and Systems. Gdynia (Poland), June 15-17, 2000, pp.533-538.
  7. E.Ivask, J.Raik, R.Ubar. Fault-Oriented Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. 7th Baltic Electronics Conference, Tallinn, October 8-11, 2000.