Lab Experiment No. 4Kirchhoff’s Laws

I.Introduction

In this lab exercise, you will learn –

•how to read schematic diagrams of electronic networks,

•how to draw and use network graphs,

•how to transform schematics into actual component connections,

•correct ways to layout a breadboard connection of a network,

•how to connect the DMM to network components, and

•the verification of KCL and KVL.

II.Experiment Procedure

Four resistive networks N1 through N4 are shown on the following pages. Each network is accompanied with its oriented graph, a simplified connection diagram, and a photo of its suggested breadboard layout. Your job in this lab experiment is to fill out the three tables included with each network with the following data: (where ‘x’ denotes the network number; eg, x = 1 for network 1, x = 2 for network 2, etc.)

(a)Table x.1 (variable map) – measure and record

i.the value of each network element,

ii.the voltage across each network element with node polarities, and

iii.the current through each voltage source with node polarities.

(b)Table x.1 (variable map) – calculate and record

i.the current through each resistor using Ohm’s law, and

ii.the power dissipated by each element.

(c)Table x.2 (KCL) – calculate and record

i.the total current into each node,

ii.the total current out of each node, and

iii.verification of KCL at each node.

(d)Table x.3 (KVL) – calculate and record

i.the total clockwise voltage drop around each circuit,

ii.the total counter clockwise voltage drop around each circuit, and

iii.verification of KVL for each circuit.

III.Lab Report

The report for this lab experiment must be word-processed and contain the following items –

• Title Page.

•Introduction.

• Procedure.

• Results.

• Discussions.

(a)Comment with respect to accuracy versus convenience on the application of Ohm’s law to determine element current.

• Conclusion. Provide detailed comments and discussions on the items listed below for each resistor network.

(a)Does the total power dissipated equal the total power supplied? Explain why or why not.

(b)Are the network laws KCL and KVL verified? Explain any discrepancies.

• Appendix.

• References.

IV.Resistor Networks

Network N1

Figure 1.1

(a) Network N1

(b) Graph G1 of N1

(c) Component connections

Figure 1.2

Breadboard layout of N1

Table 1.1
Voltage, current, and power map for N1
Element / Specified
value / Measured
value / Element voltage / Element current / Element
power (W)
Nodes / Measured
value (V) / Nodes / Calculated
value (A)
+ / − / + / −
R1 / 1KΩ
V1 / 10V / 1 / 2
Table 1.2
Kirchhoff current law
Node / Total current
into (Iin) (A) / Total current
out of (Iout) (A) / KCL
(Iin – Iout) (A)
1
2
Table 1.3
Kirchhoff voltage law
Circuit / Total cw voltage
drop (Vcw) (V) / Total ccw voltage
drop (Vccw) (V) / KVL
(Vcw – Vccw) (V)
V1, R1

Network N2

Figure 2.1

(a) Network N2

(b) Graph G2 of N2

(c) Component connections

Figure 2.2

Breadboard layout of N2

Table 2.1
Voltage, current, and power map for N2
Element / Specified
value / Measured
value / Element voltage / Element current / Element
power (W)
Nodes / Measured
value (V) / Nodes / Calculated
value (A)
+ / − / + / −
R1 / 1KΩ
R2 / 2KΩ
R3 / 3KΩ
V1 / 9V / 1 / 4
Table 2.2
Kirchhoff current law
Node / Total current
into (Iin) (A) / Total current
out of (Iout) (A) / KCL
(Iin – Iout) (A)
1
2
3
4
Table 2.3
Kirchhoff voltage law
Circuit / Total cw voltage
drop (Vcw) (V) / Total ccw voltage
drop (Vccw) (V) / KVL
(Vcw – Vccw) (V)
V1, R1,
R2, R3

Network N3

Figure 3.1

(a) Network N3

(b) Graph G3 of N3

(c) Component connections

Figure 3.2

Breadboard layout of N3

Table 3.1
Voltage, current, and power map for N3
Element / Specified
value / Measured
value / Element voltage / Element current / Element
power (W)
Nodes / Measured
value (V) / Nodes / Calculated
value (A)
+ / − / + / −
R1 / 3.9KΩ
R2 / 1.2KΩ
R3 / 9.1KΩ
R4 / 2.2KΩ
R5 / 12KΩ
R6 / 4.7KΩ
V1 / 15V / 1 / 6
Table 3.2
Kirchhoff current law
Node / Total current
into (Iin) (A) / Total current
out of (Iout) (A) / KCL
(Iin – Iout) (A)
1
2
3
4
5
6
Table 3.3
Kirchhoff voltage law
Circuit / Total cw voltage
drop (Vcw) (V) / Total ccw voltage
drop (Vccw) (V) / KVL
(Vcw – Vccw) (V)
V1, R1,
R5, R6
R5, R2,
R3, R4
V1, R1,
R2, R3,
R4, R6

Network N4

Figure 4.1

(a) Network N4

(b) Graph G4 of N4

(c) Component connections

Figure 4.2

Breadboard layout of N4

Table 4.1
Voltage, current, and power map for N4
Element / Specified
value / Measured
value / Element voltage / Element current / Element
power (W)
Nodes / Measured
value (V) / Nodes / Calculated
value (A)
+ / − / + / −
R1 / 220KΩ
R2 / 82KΩ
R3 / 47KΩ
R4 / 150KΩ
R5 / 12KΩ
R6 / 3.3KΩ
R7 / 4.7KΩ
V1 / 5V / 1 / 3
V2 / 10V / 2 / 5
Table 4.2
Kirchhoff current law
Node / Total current
into (Iin) (A) / Total current
out of (Iout) (A) / KCL
(Iin – Iout) (A)
1
2
3
4
5
6
Table 4.3
Kirchhoff voltage law
Circuit / Total cw voltage
drop (Vcw) (V) / Total ccw voltage
drop (Vccw) (V) / KVL
(Vcw – Vccw) (V)
R1, R2,
V2, R6
V2, R3,
R4, R5
R2, V1, R3
R6, R5, R7