ES210L, Digital Circuits and Logic Design Lab

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Lab 7: 2-Bit by 2-Bit Binary Multiplier

  1. Objectives
  2. Learn what a binary multiplier is and how a binary multiplier operates.
  3. Design a binary multiplier using half-adder and implement a binary multiplier on the protoboard.
  4. Build the Verilog design and test bench programs for a binary multiplier and simulate it for the input and output waveforms.
  5. Introduction

Multiplication of binary numbers is similar to multiplication of decimal numbers. The multiplicand is multiplied by each bit of the multiplier starting from the least significant bit. Each of the resulting partial products is shifted one position to the left. The summation of these shifted partial products makes the final product (see Mano, ed. 6,Section 4.7).

A bit / B bit / Product A x B
0 / 0 / 0
0 / 1 / 0
1 / 0 / 0
1 / 1 / 1
2-bit by 2-bit Multiplier / 2-bit numbers / Example / Decimal Equivalent
Bit 2^1 / Bit 2^0
Multiplicand / A1 and A0 bits-> / 1 / 1 / = 3
Multiplier / B1 and B0 bits-> / 1 / 1 / = 3
Partial product 1-> / 1 / 1 / = 3
Partial product 2-> / 1 / 1 / 0 / = 6
Carries of previous bit-> / 1 / 1 / 0
Final product bits-> / P3 = 1 / P2 = 0 / P1 = 0 / P0 = 1 / = 9

Note that the max product value of two 2-bit binary numbers requires 4 bit positions.The subscript “0” in each case represents the lowest significant bit (LSB).

  1. Parts needed

  • A Digital Multimeter
  • A +5 V power supply
  • A breadboard/protoboardand wires
/
  • Two 7408Quad 2-input AND gates
  • One 7486 Quad XOR gates
  • Datasheets of the gates from the Internet

  1. Procedure

For your report, you can save a copy of this instruction sheet with file name “YourLastName_Binary_Multiplier_Lab7.docx” & fill in the answers to the questions for submission.

  1. Fig. 1 (below, from Fig. 4.15 in Mano ed. 5) shows a 2-bit (A1A0) by 2-bit (B1B0) binary multiplier. Redraw the figure with onlyAND and XOR gates in the table below. Let the instructor check it for you to make sure you can connect it properly in the next section.


Fig. 1. Two-bit by two-bit binary multiplier
  1. Express the bit positions of the final product (P3, P2, P1, P0) in terms of A1, A0, B1, B0 with onlyAND and XOR gatesand simplify the expressions.Also express these product bits in terms of NOT, AND, OR gates.

Product Bit Positions / Express andSimplify the Product Bit Positions in terms of A1, A0, B1, B0
P0 =
P1 =
P2 =
P3 =

2.How many gates do you need for such a 2-bit by 2-bit multiplier?

Number of AND gates needed / Number of XOR gates needed
  1. Connect your diagram on the breadboard. Use AND and XOR gates, 4switches to represent A1,A0, B1, and B0 inputs, and 4 LEDs to display the status of the output product bits in proper order. Power up the circuit and check your results for the following input binary combinations. Show the circuit to the instructor when in full operation.

Switches / Product Binary Bits / Decimal equivalent of product bits P3P2P1P0
A1 / A0 / B1 / B0 / P3 / P2 / P1 / P0
0 / 0 / 0 / 0
1 / 0 / 0 / 1
1 / 1 / 1 / 0
1 / 1 / 1 / 1
Compare and explain your P3P2P1P0 result for A1A0B1B0=1011 with the formula obtained in Part D1.
  1. To simulate the circuit in Fig. 1, write a Verilog design program, called two_bit_multiplier.v, and the test bench program in the table below and compile it to ensure it is error-free. Use G0, G1, G2, G3, etc., to identify instances of the gates, and w0, w1, w2, w3, etc., to identify the wires. Include the above four combinations for A1, A0, B1, B0 with 50 ms delay between each combination entry in the table. Then, simulate the program to display the waveforms of the input and output bits P3, P2, P1, P0 and copy the display in the table below. Show your displays to the instructor.

// two_bit_multiplier.v program module / // two_bit_multiplier_tb.v program module
Waveforms of inputs and outputs
  1. Feedback/Comments (your comments will help improving this lab)

Was the instruction clear enough? / 1%
Any error? / 1%
How difficult was it for you? / 1%
Do you have any observations to make? / 2%
  1. Report
  2. Fill in the answers and Verilog programs and waveforms in the tables above.
  3. Submit your report by the following Saturday 12 PM.

Dr. Ali Kujoory10/13/20181