0.18m CMOS 2GHz Error-Correcting Encoder

MASAHIRO SASAKI†, MAI NOZAWA‡, TAKASHI MATSUMOTO‡

†Advanced Research Institute for Science and Engineering,

Waseda University

‡Department of Electrical Engineering and Bioscience,

Waseda University

‡Graduate School of Science and Engineering,

Waseda University

3-4-1 Ohkubo, Shinjuku-ku, Tokyo, 169-8555

JAPAN

Abstract: With the demand of speeding up conversion time,flash A/D converters employ short gate length processes and reduced supply voltages. Therefore, errors generated in the thermometer code, which is the output of the comparator array,cannot be avoided because of various noises or device mismatches. Usually, these errors are corrected by the encoder. In this paper, a high-speed encoder is proposed. This encoder corrects output errors,using a “twin ROM encoder,” which incorporates NMOS for all ROM switches. Using NMOS reduces the size and improves the speed. The 6-bit encoder dissipates 6.2mW at 2GHz operation using a power supply of 1.8V and 0.18m CMOS technology.

Key-Words: - Encoder, Error correction, ROM, Twin ROM, Flash A/D converter, High speed

1Introduction

In an n-bit flash A/D converter, 2n–1 comparators arranged in a line compose an array. As the power supply voltage is reduced and the resolution is increased, the margin of the analog input signal and reference voltages VREF compared by comparators becomes narrow, and the comparator array may output thermometer code with errors. These errors will distort the final digital signal conversion and degrade the linearity of A/D conversion. Usually, the encoder must correct the error. Since the error-correcting encoderconsists of logic circuits that areinaccurateat high speeds [1], [2] (Fig. 1), a ROM encoder is used. However, the error-correcting rate using a typical ROM encoder is low, soby using a “twin ROM encoder” [3] the error-correcting rate has been increased. In this paper, we reduced size and improved speed by incorporating a twin ROM encoder that can perform 6-bit operation at 2GHz and employs NMOS for all the ROM switches with a 1.8Vpower supply in 0.18m CMOS technology. By using this encoder, we will be able to implement a 6-bit 2Gs/s flash A/D converter.

Section 2 describes the fundamental structure of the twin ROM encoder. Section 3 proposes the new twin ROM encoder, using NMOS switches, in order to solve the problem of conventional structure. Section 4 shows high speed Adder for calculating two outputs of each ROM. Section 5 presents the layout of the proposed circuit and the result of the simulation. Section 6 concludes with a summary of the paper.

2Conventional Twin ROM Encoder

Although theROM encoder usesa two-input AND for row selector (i.e. address decoder) in conventional encoder (Fig. 2), inaccurate thermometer code greatly influences the output. An improved ROM encoder commonly uses a three-input

Fig. 1Logic Encoder

three-input AND for row selector to correct this error [2]-[4]. A three-input AND can correct the error to someextent. However, large errorsin thermometer code will not be corrected completely. To resolve this, a more effective error correction is achieved using “twin ROM encoder”depicted in Fig. 3.

The leftside of the twin ROM is the same as a basic ROM, using a three-input AND for row selector. PMOS switches charge bit lines to the initial state ‘1’ and NMOS switches discharge bit lines with the row select signal.

The right side is the opposite of the left. The right side is composed of NMOS switches that discharge bit lines to the initial state ‘0’, and PMOS switches which charge bit lines with the inverted signal output from the row selector. That is, if the row select signal is ‘1’, the PMOS connected to that row select line makesthe bit line output ‘1’.

Although the output from the left side and the rightside sections are the same if regular thermometer code is input, they are different from each other if thermometer code with error is input. A three-input AND row selector can correct the error to some extent, but cannot entirely correct it. Then, in twin ROM encoder, errors are reduced by adding two outputs in the adder and abandoning the LSB.

Table 1compares the error correction of a two-input AND row selector ROM, a three-input AND row selector ROM, and a three-input AND row selector twin ROM.

Fig. 2Two-input AND row selector ROM Encoder

Fig. 3Three-input AND row selector Twin ROM Encoder

Table 1Comparison of Error Correction

∙∙∙ / ∙∙∙ / ∙∙∙ / ∙∙∙ / ∙∙∙
Thermometer
Code / 26
25
24
23
22
21
20
19 / 0
0
0
1
1
1
1
1 / 0
0
0
1
0
1
1
1 / 0
1
0
0
1
1
1
1 / 0
0
0
1
0
1
0
1
∙∙∙ / ∙∙∙ / ∙∙∙ / ∙∙∙ / ∙∙∙
2-AND ROM / 010111 / 010101 / 010000 / 010001
0LSB / –2LSB / –7LSB / –6LSB
3-AND ROM / 010111 / 010111 / 010000 / 010111
0LSB / 0LSB / –7LSB / 0LSB
3-AND twin / 010111 / 010111 / 010111 / 010111
0LSB / 0LSB / 0LSB / 0LSB

3Proposed NMOS Switch Twin ROM Encoder

Conventional twin ROM encoder have two problems.

First, conventional ROM encodersoperate irregularly at high speeds when bit lines are not completely charged. The reason is that when bit lines are being charged, any ‘1’ row select signal tries to discharge the corresponding bit lines and the lines data

Fig. 4Proposed NMOS Switch Twin ROM Encoder

depends on the resistance ratios of the charging and discharging switches.

In our proposed circuit shown in Fig. 4, a two-input AND is inserted between the three-input ANDand the ROM. While PMOS switches for charging bit lines are ON by CLK_B, CLK_R operates so as to keep row select signals turned OFF, which eliminates the conflicting situation of conventional twin ROM encoder. Moreover,the output of bit lines has to be latched by clocked inverters with timing opposite to CLK_B.

Next, conventional twin ROM encodershave the problem that NMOS switch is used on the leftside of the ROM, on the other hand PMOS switches are used on the right. Since the electron mobility of NMOS differs from PMOS, PMOS needs to be two to three times larger than NMOS if NMOS and PMOS are to operate at the same speed. This causes new problems such as different transmission delays because of different parasitic wiring capacitance due to different layouts. In this proposed circuit, this problem is solved by using NMOS switches on both sides (ROMs) to make area and speed of both sides equal.Moreover, since n inverters for reversing the output of bit lines can be used instead of 2n inverters for reversing row select signals, by also using NMOS switches on the right hand, 2n inverters for reversing row select signals can also be managed with n inverters for reversing the output of bit lines by also using NMOS switches on the right side, the area is reduced.

Fig. 5Timing diagram

4High Speed Adder

With the improved ROM speed, an adder that operates at a high speed is also needed. Therefore, we use the adder shown in Fig. 6 [5]. Adder cell of each bit in Fig. 6 is shown in Fig. 7. The transmission speed of carry is improved by preparinga dedicated path for producing carry, enabling a very high-speed adder to be constructed.

Fig. 6High Speed Adder

Fig. 7Adder Cell

5Layout and Simulation

We have designed a6-bit 2GHz NMOS switch twin ROM encoder using 0.18m CMOS technology. The area and the parasitic capacitance of devices and wiring were decreased by using NMOS switcheswith a gate finger structure and coupling the sources of NMOS switch with the source connected to the next bit line. They were also reduced by being made equal height of the two-input AND, the inverter that is the second half of the three-input AND row selector, and the row select line of the ROM.

An appropriately sized three-input NAND, which is the first half of a three-input AND, is placed just behindthe comparator to minimize the wiring capacitance that the comparator array must drive. Fig. 8 illustrates the layout of one row of ROM, Fig. 9 depicts the layout and block diagram of the entire encoder.

When the three-input NAND cell height is decided according to the front comparator, the actual area of the entire encoder is 44353m2:

Total Area
= Area(three-input NAND)
+ Area(wiring)
+Area(Inverter, two-input AND,
NMOS Switch Twin ROM, Latch, Adder)

Total Area

= 9201 (three-input NAND)

+ 23698 (wiring)

+ 11454 (Inverter, two-input AND,

NMOS Switch Twin ROM, Latch, Adder)

= 44353 m2

Fig. 8One row of ROM

Fig. 9Layout and Block diagram of the entire Encoder

We performed a simulation on the extracted net list of the encoder of Fig. 9. Power consumption of 6-bit encoder was 6.2mW operating at 2GHz using a 1.8V supply.

6Conclusion

This paper proposeda new three-input AND NMOS switch twin ROM encoder to efficiently correct thermometer code errors at high speeds.

Although it is difficult to increase speed utilizing a conventional circuit, we could implement a high-speed encoder by minimizing device size using NMOS for all ROM switches, by restricting the ON time of NMOS switches so as not to overlap the charge time of bit lines, and by using high-speed adder.

In the layout, the area and the parasitic capacitance of devices and wiring were decreased by using NMOS switcheswith agate finger structure and coupling the sources of adjacent NMOS switches. Furthermore, the heights of the two-input AND, the inverter that is the second half of the three-input AND row selector, and the row select line of the ROM were made identical to reduce the area of the entire encoder. Besides, an appropriately sized three-input NAND, which is the first half of the three-input AND, is placed just behindthe comparator to minimize the wiring capacitance that the comparator array must drive.

These various improvementsresulted in a high-speed, small 6-bit 2GHz NMOS switch twin ROM encoder using a power supply of 1.8V and 0.18 m CMOS technology. The power consumption is 6.2mW with a 1.8V power supply and 6-bit 2GHz operation.

A 6-bit 2Gs/s flash A/D converter is therefore feasible.

Table 2 presents the characteristics of this proposed circuit.

Table 2Encoder Performance

Technology / 0.18m CMOS
Total Area / 44353 m2
Resolution / 6-bit
Operating Rate / 2 GHz
Power Supply / 1.8 V
Power Consumption / 6.2 mW

Acknowledgement

This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence Design Systems, Inc. and has been The device was fabricatedwith the collaboration by Hitachi Ltd. and Dai Nippon Printing Corporation.

References:

[1] Peter C.S.Scholtens, Maarten Vertregt, ‘A 6-b 1.6-Gsample/s Flash ADC in 0.18-m CMOS Using Averaging Termination,’ IEEE Journal of Solid-State Circuits, Vol. 37, Dec 2002, pp.1599-1609.

[2] Clemenz L. Portmann, Teresa H. Y. Meng, ‘Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters,’ IEEE Journal of Solid-State Circuits, Vol. 31, No. 8, Aug 1996, pp. 1132-1140.

[3] Masao Ito, Takahiro Miki, Shiro Hosotani, Toshio Kumamoto, Yukihiro Yamashita, Masaki Kijima, Takashi Okuda, Keisuke Okada, ‘A 10bit 20MS/s 3V Supply CMOS A/D Converter,’ IEEE Journal of Solid-State Circuits, Vol. 29, No. 12, Dec 1994, pp. 1531-1536.

[4] Koen Uyttenhove, Jan Vandenbussche, Erik Lauwers, Georges G. E. Gielen, Michiel S. J. Steyaert, ‘Design Techniques and Implementation of an 8-bit 200-MS/s Interpolating/Averaging CMOS A/D Converter’, IEEE Journal of Solid-State Circuits, Vol. 38, No. 3, Mar 2003, pp. 483-493.

[5] Kiyoshi Kitamura, Mikio Yagi, Kazuo Taki, ‘A super high-speed adder in the “Plastic Hard Macro Technology”,’ Information Processing Society of Japan Journal, Vol. 42, No. 04, 2001.