Adaptive Noise Cancellation System
A simple active noise cancellation system to counter a specific noise signal.
Prepared By: Irtaza Ahmed
Michael Foster
Michael Loper
Date: September 20, 2015
Table of Contents
Overview
Needs Statement
Objective Statement
Description
Marketing Picture
Requirements Specifications
Customer/Marketing Requirements
Engineering Requirements
Concept Selection
Brief History
Survey of Existing Systems/Components
Design
Overall system and Subsystems
Figure 1: Level zero block diagram representing the FPGA, inputs, and outputs.
Figure 2: Level one block diagram of the Virtex-5 FPGA.
Figure 3: Level three block diagram of a general DSP slice used as a Multiply Accumulate Unit.
External Hardware
Adaptive Algorithms
Figure 4: Stem plot of a sinusoidal signal
Figure 5: Block diagram of a third-order FIR filter implementation
Figure 6: Top-level block diagram of the adaptive noise cancelling algorithm.
Circuits and Assemblies
Figure 7: Pin configuration of the microphone.
Figure 8: Block diagram of the I2S hardware needed.
Figure 9: USB Controller on the Virtex-5.
Figure 10: Audio Codec on the Virtex-5.
User Interface and Controls
Figure 11: User interaction state diagram.
Figure 12: Prototype of user interface.
Engineering Standards
Multidisciplinary Aspects
Background
Outside Contributors
Constraints and Considerations
Extensibility
Manufacturability
Societal Context
Reliability
Health and Safety Issues
Economic Context
Intellectual Property
Cost Estimates
Testing Strategy
Risks
Algorithm
Board
Interface
Milestone Chart
Appendices/References
Adaptive Noise Cancellation System Page | 1
Overview
Needs Statement
Noise cancellation is a thriving and popular industry in today’s society. As we push forward in this modern era, technologyis becoming an ever growing distraction and hindrance in the flow of daily life.The need to unplug and disconnect becomes evident. Noise cancellation headphones can help to provide that relaxing commute and block out the uncomfortable noises surrounding travel via aircraft, trains, or even automobiles. Larger noise cancellation systems can also remove distracting background noises to provide that perfect laboratory or educational working environment. A small and affordable system is needed to counter unwanted noise signals and to create a quieter and more comfortable environment for the customer.
Objective Statement
The objective of this project is to research, design, and implement an active noise cancellation system that will be affordable to a general audience. The device will produce signals to achieve destructive interference with an input signal. The input signal will represent unwanted noise outside of a desired frequency range. The system will be primarily designed for use with headphones, but it will be adaptable for use in more complex applications such as a speaker system. One possible application of the system would be a laboratory environment which contains noisy machines or power tools. In this application, the system would be connected to a set of speakers in the laboratory, and the system would counter the noise produced by the machines or tools. Headphones could also be connected to the system, and it would function like a set of noise cancelling headphones.
Description
Adaptive noise cancellation systems actively produce counter signals to block out undesirable signals at specified frequencies or frequency ranges. The adaptive noise cancellation system for this project will be built using two microphones, a headset, and a Field Programmable Gate Array (FPGA). There will be one external microphone that will take in the noise signal to be processed by the FPGA. The FPGA will then use the FIR (finite impulse response) and LMS (least mean square) algorithms to attempt to produce the necessary counteractive signal. The FPGA in turn sends the counter signal to the headset. The signal from a feedback microphone in the headset will be used to produce the next iterations of the algorithm until a desired noise signal degradation threshold has been reached. If the system is used with a set of speakers, the feedback microphone would be placed in the region where noise cancellation is desired.
Marketing Picture
Requirements Specifications
Customer/Marketing Requirements
- The system should be safe.
- The system should be small.
- The system should be affordable.
- The system should correctly cancel all undesired sounds.
- The system should use standard audio connectors.
- The system should be easy to maintain and upgrade.
- The system should be easy to move.
- The system should be durable and have protection against damage.
- The system should not produce much heat.
- The system should have a simple interface.
- The system should be aesthetically pleasing.
- The system should be energy efficient.
- The system should be able to accept input noise.
- The system should reduce the volume of undesired sounds quickly.
Engineering Requirements
Marketing Requirements / Engineering Requirements / Justification10 / A. User interface will consist of a single on/off switch. / The system does not need to be configured by the user.
6 / B. The design process will be well-documented. / Documentation is important for any future work that may be done on the project. It can also be used as a resource for other projects.
4,10 / C. Upon power up, the system will counteract noise signals which fall between 40 Hz and 80 Hz. / This chosen frequency range signifies all the unwanted noise the system will need to counter-act. This range does not need to be configured by the user.
5,6 / D. The output of the system will be a 3.5 mm headphone jack. / The 3.5 mm headphone jack is the standard for many electronic devices.
3 / E. The cost of the system will not exceed $1000 per academic unit. / Keeping the cost of the system to $1000 per unit will help make the system more affordable and marketable to customers.
1,2,7,8,11 / F. The processor and all internal connections must be enclosed in a hard case with dimensions no more than four inches larger than the dimensions of the FPGA on each side. / Keeping the system enclosed in a case that is about the size of the board used will ensure that the system is safe, small, easy to move, durable, and more aesthetically pleasing to the customer.
5,8 / G. The system must contain two microphones, an FPGA, necessary wires, a headset, and a hard case. / The basic components are what the system needs to work.
4 / H. The microphones must be able to detect frequencies in the range from 20 Hz to 20 kHz. / This is a basic need of the system so that it can detect the noise signals which must be countered.
3,9,12 / I. The system must consume less than 0.3 kWh on average. / With a low power consumption, the product is more affordable.Low-power systems also do not produce much heat.
1,12 / J. The system must not exceed a peak instantaneous power usage of 10 W. / Putting a cap on the peak power usage of the system will act as a safety feature to keep it from tripping breakers or drawing more than a desired amount of power at any given point in time. This will also ensure that the system stays energy efficient.
4 / K. A drop in the volume of the noise signal must be detected by 85% of individuals who test the system. / The noise signal will not be completely countered; however, a drop in volume should be detectable by a customer with average hearing capabilities.
4,14 / L. The delay between the point at which the system is powered on and the noise signal is cancelled will not exceed 3 seconds. / If the delay is too long, there will be an extended period of unpleasant ringing while the signals are not 180 degrees out of phase. If this period is excessively long, it could become unpleasant to the customer.
1,4 / M. The volume of the counter signal will not exceed 85dB. / To produce a pleasant output sounds the counter signal must be relatively inaudible by humans. Also, the system should never produce a sound that could be painful or cause harm to the customers’ ears.
13 / N. The system must be able to interact with two microphone inputs either through line inputs or GPIO pins. / This is a fundamental part of the system’s operation. The system must be able to take in the noisy signal and have a feedback loop for the algorithm to work.
Concept Selection
Brief History
In the 1990s, personal active noise cancelling systems consisted of a pair of headphones connected to a processing unit. This processing unit was either encased in a hand-held module or it was integrated into a stationary object such as an armrest in an airplane seat. Modern noise cancelling headphone designs are now embedding the processors in the headphones. These processors could be high-end DSPs (Digital Signal Processors) or ASICs (Application Specific Integrated Circuits).
Survey of Existing Systems/Components
Silentium is a company that specializes in noise cancellation systems and solutions. One of its products is the “ActiveSilencer Enclosure.” This noise cancellation device is specifically designed to minimize the noise pollution from servers by up to 10 dB without causing any thermal or cooling degradation. Silentium also has the “S-Cube Development Kit” that is designed to allow an individual to create their own custom noise cancellation solution. Silentium suggests the S-Cube can be used in applications such as reducing fan noise or irritable noise created by electronics in general. This system costs $4,500, which is well over the cost of our system. Silentium claims that its products can cancel frequencies from low range signals up to 1800 Hz. Its systems can also counteract multiple frequencies rather than just a single tone.
There are a wide array of noise cancellation headphones in today’s market. There is a pair of MDR ZX110NC SONY headphones that claims to reduce up to 95 percent of ambient noise produced by the office, airplanes, and trains. These headphones are at a low cost of around $40. These headphones are for the specific use of providing comfort for travel. Most of the headphones on the market that are used to give quality sound and combine the use of passive and active noise cancellation start at $250.
Our system helps to provide an affordable solution to general noise cancellation. The system we have proposed will cost less than many of the noise cancellation systems available, while still providing the ideal quiet environment. Our device is expandable beyond headphone application, but each system will be more affordable than existing active noise cancellation systems.
‘
Design
Most noise cancellation systems use microphones, FIR filters, cancellation algorithms, and speakers or headphones. We will be following this model that has succeeded in the past.
Figure 1 shows the two inputs and outputs for microphones and one output for the headphones. The board will be programmed through a PC using the JTAG to USB communication. The board will also be connected serially to the computer for testing purposes, and oscilloscopes will be used on the microphone communication lines. The inputs for the microphones will be the inputs and outputs for the bidirectional communication required by I2S.
Figure 1: Level zero block diagram representing the FPGA, inputs, and outputs.
Overall system and Subsystems
Since we will not have the funds to produce an ASIC design, the only viable processor solutions for this project are a DSP or an FPGA. One advantage of an FPGA is that it can perform multiple operations at a time due to its use of parallelism, where a DSP processor performs one instruction at a time. However, as filter order increases, the delay in the FPGA increases due to register-to-register delay, and the speed increase due to parallelism with be overcome. Research showed the tradeoff here and compared an implementation of a filter of order ten implemented on an FPGA processor versus on a DSP processor of similar specifications[8]. The DSP processor took 2.3 µs to update the weights on the adaptive filter and the FPGA took 67 ns [8]. This difference is astounding for a filter of order ten.
From research it is has been determined that we will require a filter order in the range of 8 to 64 [8]. Most FPGAs will have the resources to do the computations for filters of these orders faster than similarly specified DSPs. Also, if the chosen FPGA has on-board DSP slices, it will produce the desired results very rapidly. For these reasons, we have decided an FPGA will be the right fit for our implementation of an adaptive noise cancellation system.
We also believe that an FPGA implementation will give our design a higher degree of flexibility. This flexibility will become especially important if we are able to expand the application of our design to noise cancellation in complex environments such as small rooms. This complex implementation would likely require a large number of parallel computations in order to counter complex combinations of noise signals in real time.
There are a wide variety of FPGAs in today’s market. The following table was produced by obtaining a subset of FPGAs that have successfully been used in existing adaptive noise cancellation systems or projects.
Board / Number of Multipliers / Slices / LUTs / DSP Slices / CostXilinx Virtex-2 Pro XC2VP30 / 136 (18 x 18) / 13,696 / 27,392 / No / $1,799 or $399 (Academic)
Xilinx Virtex-5 XC5VLX110T / 64 (25 x 18) / 17,280 / 69,120 / Yes / $2,199 or $799 (Academic)
Xilinx Spartan-3E XC3S500E
(Starter Kit) / 20 (18 x 18) / 4,656 / 9,312 / No / $199
ALTERA DE2 CYCLONE-II EP2C5 / 13 (18 x 18) / 2304 (est) / 4,608 / No / $137
NI cRIO-9104 / 96 (18x18) / 14,336 / 28,672 / No / $3,559
The consensus of the existing research is to use an LMS adaptive filtering algorithm that utilizes FIR filters[2, 11, 13, 15, 16]. The desired FPGA must have enough slices to hold a high order FIR filter implementation. The higher the filter order, the more slices will be required. The desired FPGA must also be able to multiply and add rapidly to perform the LMS filter iterations at a desired rate. From the research, it was determined that for a filter length of 512, around 1600 slices are needed for a board with no dedicated DSP slices [2, 5, 8]. Dedicated DSP slices on an FPGA contain at least one multiply and accumulate unit. These units are capable of performing consecutive multiplication and addition operations quickly and efficiently. These units will therefore directly aid in the speed of an LMS algorithm due to the numerous multiply and accumulate operations required. The desired filter length will be based onthe input frequency range of the noise signals, which the system is capable of countering. Generally, an FIR filter of order 8 to 64 was used in the successful projects to cancel a 60-Hz signal. This gives a range of around 180 to 330 slices required for the general boards and even fewer slices needed for a board with dedicated DSP slices. The research also suggests that the reduction of resources utilized by the board from using DSP slices will reduce the total power consumption by up to 50% [8]. Speed is the most important requirement our system needs, and the Xilinx Virtex-5 provides the extreme speed and efficiency needed to satisfy all the system requirements while leaving room to successfully grow into a more complex cancellation system.
Figure 2shows that the FPGA will take in digitized data points from the external MEMs based microphone and give them to the DSP slices inside the FPGA (The MEMs microphones have analog to digital converters to give the digitized data desired.). The FPGA will use the LMS algorithm to produce a series of coefficients, WN's, from the input signal and the feedback signal. These coefficients will be given to the DSP slices to perform calculations on the input signal to produce the counteractive signal. The combination of the signals will be given to the audio codec, which sends the analog version of the output signal out to the headphones. The other MEMs based microphone inside the headset will act as a feedback system to send the signal back into the FPGA, which will then use the LMS algorithm to generate, if necessary, the next iteration of the coefficients to produce even less error. This process is repeated until the error reaches the desired threshold. Both microphones use the I2S protocol to talk to the FPGA through the GPIO pins. This produces the need for two microphones and one line output for the headphones.
Figure 2: Level one block diagram of the Virtex-5 FPGA.
Figure 3shows how the DSP slices can be set to easily multiply and accumulate results, which is what is needed for the LMS algorithm to work efficiently. The DSP slices will calculate the filter error from the new filter weights generated by the processor and the input signal.
Figure 3: Level three block diagram of a general DSP slice used as a Multiply Accumulate Unit.
External Hardware
Two microphones are needed for the system, one to detect the noise, and another to collect the feedback signal. Current noise cancelling headphone systems include these microphones mounted on the inside and outside of the headphone ear-cup. The external microphone picks up the noise signals such as traffic or conversations. The feedback microphone is placed inside an ear-cup of the headphones to create a feedback loop for active noise control. In this project, the outer noise detection microphone will be an external, handheld microphone. The table below shows some of the microphones that are being used in the noise cancellation applications today.
Microphone / Frequency Response / Output / SNRHigh SPL Analog Microphone / 6 Hz -20 kHz / Analog / 63
Ultra-low current-low noise microphone / 75 Hz - 16 kHz / Analog / 64
Omnidirectional MEMS Microphone with Bottom Port / 60 Hz -15 kHz / I2S / 61
Low-Noise Microphone / 45 Hz – 20 kHz / I2C / 65
The best-suited microphone for this project is the Omnidirectional Microphone with Bottom Port and I2S output from InvenSense. The frequency response and the signal-to-noise-ratio (SNR) were two major factors in deciding which microphone would work best for this project. Based upon our specifications, we decided that a microphone with a frequency response from 60 Hz to 15 kHz would be sufficient.In addition, the SNR should be around 60 dB to sufficiently pick up the sound of normal human voice over three feet [31]. Therefore, the Omnidirectional Microphone from InvenSense was a good match for this project. The microphone’s sensitivity to a sound source does not change with the position of the source due to its omnidirectional nature.TheI2S output interface also allows the microphones to be connected directly to the FPGA without the need for an audio codec in the system.Finally, the frequency response of this microphone is between 60 Hz to 15 kHz, which is sufficient enough to produce an accurate representation of the original sound.