Designing an Arithmetic Logic Unit (ALU)

1

EX2: Designing an arithmetic logic unit (ALU)

EX 2EX 1DIGITAL CIRCUITS AND SYSTEMS

Designing an arithmetic logic unit (ALU)

1.1Cooperative group

TEAM NUMBER: ______

DUE DATE: ______1st review due date: ______

STUDY TIME:

Study time
(in hours) / Group work / Classroom and laboratory sessions / Sessions out of classroom
Individual / Student 1
Student 2
Student 3

STATEMENT:

My signature below indicates that I have (1) made equitable contribution to EX 2 as a member of the group, (2) read and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document, and (3) acknowledged by name anyone outside this group who assisted this learning team or any individual member in the completion of this document.

Today’s date: ______

Active membersRoles: (reporter, simulator, etc.)

(1)______

(2)______

(3)______

Acknowledgement of individual(s) who assisted this group in completing this document:

(1)______

(2)______

1.2Abstract

Explain here the most significant developments, results or conclusions about the exercise. Use the remaining space in this sheet (200 words maximum).

(This section is mandatory. You must complete it in order to get a mark.)

CONTENT

Designing an arithmetic logic unit (ALU)

1.1Cooperative group

1.2Abstract

1.3Description

1.4Topics

1.5Part 1: Introduction and block diagrams

1.5.1The “simple machine”

1.5.2Concept of an ALU, design specifications and block diagram

1.6Part 2: Installing and using Altera Quartus-II (or Lattice Diamond or Xilinx ISE)

1.7Part 3: Development and functional simulation of combinational blocks

1.8Part 4: Chip programming and prototyping using training boards

1.9Problem solution (títol 2)

1.9.1Part 1 (títol 3)

1.10References

1.11Study plan to solve the exercise

1.12Topics and activities checklist

1.13Grading grid

1.14Questions in solving EX2

1.3Description

In this second exercise, a specific application of combinational circuits is designed and implemented into a complex programmable logic device (CPLD) or a field programmable gate array (FPGA), in this case, an arithmetic and logic unit (ALU). In Part 1, the ALU architecture, attending its initial specifications, is devised. In Part 2, the top-down VHDL-only project, for the AlteraQuartus-II or the Lattice ispLEVER Starter software, is prepared and synthesised until the final configuration files are obtained without errors. In Part 3, testing methodologies, relying on ALDEC ActiveHDL or Mentor Graphics ModelSim, are used to verify the entity. And finally, in Part 4, a training board, Altera (UP2, DE2) or Lattice (MachXO USB) is used to implement and run the final prototype.

One of the main characteristics of the proposed design is that it has to be carefully planned (structured) due to the large number of blocks involved. Essentially, the project will consist in many VHDL source files to define components, which afterwards have to be instantiated following a hierarchical top-down design approach.

1.4Topics

The following topics have been listed from the course’s specific and cross-curricular learning objectives[1]: #4 and #8. After studying Chapter 1 and successfully completing all the assignments in this task, you will be able to:

------Part 1------

1. Read the basics of the “simple machine” already studied in previous subjects on computers.Produce block diagrams for designing the combinational entities in the “simple machine” (ALU and program address generator).
2. Programming subtractions by means of a series of simpler operations (this is a sequential algorithm).
3. Install AlteraQuartus II, Lattice Diamond, or XilinxISEdesign tools to implement VHDL-only projects. Run demonstration examples to check the software.Use register transfer level (RTL) and technology views as a help to debug the design through the synthesis process and to clarify the VHDL programming style.
4. Explain by means of a concept map or a power point presentation, the basic technological details of a CPLD or a FPGA and the way they are programmed.

------Part 2 ------

1. Design a VHDL project for the design of the ALU using elemental blocks as components in a top-down hierarchical and structured design.
2. Install (if not yet for EX1B) the ModelSim or ActiveHDLsimulators to verify the VHDL project. Run a demonstration example to check the software.Verify the ALU and the other combinational designs performing functional simulations.

------Part 3 ------

1. Run the design flow, which essentially consist of: (1) VHDL source files; (2) functional simulation; (3) pin assignment; (4) synthesis; (4) gate-level simulation; (5) device programming; and (6) prototype verification. Implement and check the final design into a CPLD/FPGA training board.

------Part 4 ------

1. Write and share through the Internet (your Google Sites ePortfolio) a written solution to the problem which has to follow this template (as in EX1). The quality criteria from this document have to be also considered when designing the project. Complement also the planning schedule, your self-assessment mark and your reflections, and remember to sum up your study time using the spreadsheet which can be viewed at your ePortfolio.

1.5Part 1: Introduction and block diagrams

1.5.1The “simple machine”

Here you are information about the “simple machine” project which is in use at the 2G subject Projecte de Programació (PP) and at the 1G subject IntroduccióalsOrdinadors (IO).

Fig.1 The “maquinasenzilla” [2]

This digital machine is indeed a very simple microprocessor which operates by means of assembly language. By now, just read to grasp the very basic ideas because we will focus on the combinational sections, essentially, (1) the program address generator and (2) the ALU block.

a) / b)

Fig.2a) The microprocessor’s combinational section which have the mission to generate the addresses to fetch instructions from the memory. b) An improved (Visio) schematic of the septuple multiplexor of 4 channels.

a)Invent a detailed block diagrams and hierarchical designusing combinational components, if necessary, for the section pictured in Fig. 2.The Fig. 2b is simple a better drawing for the septuple 4-channel multiplexer.

1.5.2Concept of an ALU, design specifications and block diagram

The ALU is the main component of a datapath or operational unit which also contains data registers to store operands and results. Registers will be the object of Chapter 2 because they can be specified as finite state machines (FSM), and a datapath will be designed in Chapter 3 as an example of a dedicated processor.

b)Search information about the main characteristics and utility of an arithmetic logic unit (ALU) block. Summarise them through a concept map[5].For example, read the datasheet of the 74LS181 chip, a 4-bit ALU in the classic Low-power Schottky (LS)tehcnology.

c)Considering the entity to be designed and its specifications in Fig. 3, invent a block diagram for the ALU, based on a top down and hierarchical design. Vector ALU(1..0) has to be used to select the operation to be performed. The output Zis what is called a “flag”, and in this case: Z = 1 when the result of any operation is zero. Check your ALU diagram testing some operation examples. Notice that we have complicated a little bit our ALU just using the “11” to multiply the byte-wide operands.

d)Explain the algorithm and sequence of operations which may be necessary to “program” a subtraction of the 2 operands (R = A – B). Only resources from the ALU have to be used.Read old ED Unit 1.3 to learn about the two’s complement convention (2C) to represent integer numbers. Design another flag (V) to signal when the result of an operation overflows.

ALU(1..0) code / Operation / Flags affected
00 / R = A + B / Z
01 / R = A xor B / Z
10 / R = B / Z
11 / R (15..0) = A(7..0) × B(7..0) / Z

Fig.3 ALU symbol and specifications. Note that for the multiplier, the ALU only accepts 8-bit wide inputs to produce a 16-bit wide output.

1.6Part 2: Installing and using AlteraQuartus-II (or Lattice Diamond or Xilinx ISE)

e)Follow instruction in Unit 1.11 to install Quartus-II software. Check the software by running the proposed tutorial sample design uploaded in the web or just start a new project using a VHDL file from the EX1. Print the RTL netlistview as a picture and explain its main parts.Explain the difference between the RTL netlist and the technology netlist.

f)Follow the design flow and download the configuration file for the tutorial example into the UP2 training board.

g)Explain by means of a concept map or a power point presentation, the basic technological details of a CPLD, for example the Lattice ispMach4128V, or a FPGA, for example the AlteraCyclone II EP2C35F672C6, and the way they are programmed.

1.7Part 3: Development and functional simulation of combinational blocks

Here in this section a top-down hierarchical approach will be considered. There are several circuits to be designed with different levels of complexity. Thus, start with the top and go into every single component trying to design it using simpler blocks and elemental components from the library. Be neat and organised. Firstly, draw a diagram or a logic schematic to represent the block been designed for documentation and clarification purposes when discussing the architectures with your team mates. The idea is very simple: never write VHDL code without having a graphical representation of the circuit been designed. Remember to name all the circuit or schematic signals and ports before attempting to code in VHDL. Once you already have a circuit structure, start coding it from bottom to top implementing useful blocks or components with the aim to be used later on in new and more complex designs. Indeed, every component has to become a project in itself with a simulation and verification procedure included, before attempting to use it in larger projects.

h)Design the project for circuits in Fig. 2. Perform a functional simulation to validate it using timing diagrams to show signal activity over time. The simulation project has to be placed into a new folder under the project’s upper general directory.

i)Design the VHDL code for every ALU subsystem (Fig. 3) and validate them all exemplifying some particular operation. Simulate your ALU blocks starting with the simpler ones. Document the simulation process, from the input vector generation to the final timing diagrams showing input and output activity and explaining the main issues.

In order to validate every one of the ALU subsystems, the code has to be simulated. To do this job, there are several options depending on the tools. For instance, AlteraQuartus II (or XilinxISE)has their own embedded simulator tools, but Lattice Diamonddo not have it. Therefore, to make your design more compatible and vendor independent, you may decide not to use the integrated simulators and instead, install independent professional simulation tools, like Mentor Graphics ModelSim or AldecActiveHDL, which both have student editions.

j)Install ModelSim, or Active HDL. First of all, run the functional simulation of a simple example to get used and learn about the simulation procedures. This section may be already done in EX1B. So, if this is the case, just bypass it.

1.8Part 4: Chip programming and prototyping using training boards

Once the code has been functionally verified using simulator tools, the design flow continues: (1) assigning pins, (2) synthesising the logic circuit into a specific programmable logic device, and (3) downloading the programmable device configuration file onto the training board to check the prototype.

As in previous sections, you do not need to have the ALU design completed, because a final prototype can be also generated even for an ALU section, for example for the unsigned adder. Thus, start which a very simple design and complicate it step by step while you are getting used to the tools and you are gaining confidence in the results.

k)Depending on the training board[2] and the specific vendor tool which were chosen, assign pins to the ports of your VHDL-based design and run the automated synthesis process until the configurations files are obtained free of errors. Download then into the target chip and training board and check your final design.

l)And, as always, document and report very carefully all your design steps paying special attention in the written text, figures, tables and references.

1.9Problem solution (títol2)

1.9.1Part 1 (títol3)

Part 1.1(títol 4)

És necessari que seguiu aquestes indicacions per qualsevol dels vostres documents en aquesta assignatura. Aprendre-les forma part de la competència de comunicació escrita. Adapteuelsvostresdocuments al formatsubministrat per aquesta plantilla.

Si alguna indicació o format no l’acabeud’entendrebé, pregunteu-nos-ho o aclariuelsdubtes, peròno lliureumai res que nocompleixiaquestesindicacionsperquè no ushocorregirem i perdreu el temps.

Afegiu aquí el vostretext(estil normal)encapçalatambtítols (Títol2 i 3 i 4), amb figures (estil “llegenda” o “epígrafe”) i referènciescreuades en el textcomaquestaFig. 4(és una referènciacreuada a la llegenda, veureu que surt en color gris quan la cliqueu)a les figures que inseriu. Fixeu-vos que la primera vegada que obrireuaquestdocument en Word 2007, no ussortiràaquestallegenda “Fig.”, així que haureu de crear-ne una, i després, encara que la esborreu,jausquedarà la referència. Veureu també que la numeració de les figures és un paràmetreautomàtic. Si seleccioneutot el document, i premeu “F9” actualitzareu tota la numeració.

També l’índex de la pag. 2 éscompletamentautomàtic. Es genera sol ( a partir de referències, índex de continguts, Inseriu un índex de continguts) i s’actualitza sol a partir també de “F9” haventseleccionattot el text de document. Éspossible que la primera vegada que l’actualitzeudesaparegui. No passa res, simplement cal tornar-lo a generar a partir del menú referències i taula de contingut.

Fixeu-vos en la Fig. 4. Les imatges han d’estarcentrades i alineadesamb el text. Si voleu posar un parelld’imatges a la mateixalínia, inseriu primer una taula d’unparell de columnes i totseguitfeu invisibles les vores. El millor que podeuferés “cut & paste” dela pròpia taula que veieu, i, canviar les figures per les vostres.

Feureferència també en el text a les fontsbibliogràfiques o de web que consulteud’aquesta manera [1] (és una referènciacreuada a l’elementnumerat [1]). Expliqueu perquè les heu consultat i quina informació útil heu trobat.

Per corregir la primera versió del vostretreball, no imprimiu ni lliureu des de les pàgines 3 a la 5. Ésl’enunciat del problema. Solscal que imprimiules 2 primerespàginesque contenenelsdetallspersonals, el resum i l’índex, i a partir d’aquestamateixapàgina6. Peròfeu-hoamb la numeració correcta. És a dir, treballeusempre sobre aquestdocument, i en tot cas, importeualtres textos que tingueucap a aquestmateixdocument i formateu-los correctament.

Insistim sobre aixòmateix: treballeusempre sobre aquestmateixfitxer per preparar la vostrasolució. Aixíusareutots els estils i formats que ja té predefinitsaquest document.

Fig. 4 Exemple de peu de figura que segueix la numeració de l’enunciat(llegenda).

Heu d’instal·lar els correctors ortogràfics en català, espanyol i anglès en el vostre paquet d’eines office.I sobretot, corregir qualsevol error mentreescriviu. Si treballeuaixòestalviareumoltafeinaalsvostrescompanys i instructors.

1.10References

Modify or add new references to this section. Follow the same format.

[1] Course wed page where to find a lot of resources for the course. Specially materials from previous editions. Go and read for example the ED Unit 2.13 on a dedicated processor (Chapter III) for multiplying numbers [retrieved 09/2010].

[2] . Resources for the “simple machine”. [Retrieved 09/2010].

[3]Unit 1.12 (ED) on concepts on arithmetic and logic units.

[4]Brown,S., Vranesic, Z., “Fundamentals of digital logic with VHDL design”, McGraw-Hill, 2005. Comment: Figure 1.7 contains an example of design flow for logic circuits and Figure 2.29 the structure of a typical CAD/EDA system.

[5]An image to define a concept map: 09/2010].

1.11Study plan to solve the exercise

Establish a study plan, a task distribution scheme and other requirements to succeed in producing a good solution when working cooperatively: flux diagrams, concept maps, schematics, tables, pictures, etc.

(This section is mandatory. It must be filled in order to get a mark.)

1.12Topics and activities checklist

Topics / Activities / Group member in charge / Comments
1 / 2 / 3

1. Invent a block diagram for the ALU of the “simple machine”.

/ a), b), c)

1. Algorithm for performing subtractions on the “simple machine”.

/ d)

1. Install AlteraQuartus II, Lattice Diamond, or XilinxISE design tools to implement VHDL-only projects. Use register transfer level (RTL) and technology views as a help to debug the design.

/ e), f)

1. Explain succinctly what are a CPLD or a FPGA and the way they are programmed.

/ g)

1. The hierarchical top-down implementation of the combinational blocks of the “simple machine” using networks of components.

/ h), i)

1. Verify the designs of the combinational blocks performing a functional simulation using ModelSim or ActiveHDL.

/ j)

1. Implement and check the final design into a CPLD/FPGA training board.

/ k)

1. Write the problem solution at your ePortfolio following quality criteria.

/ l)

1.13Grading grid

Here you are the way the exercise could be grades.

Part 1 / Part 2 / Part 3 / Part 4 / Total
a), b), c), d) / e), f), g) / h), i), j) / k), l)
Scores / 2p / 3p / 2p / 3p
Self-assessment
Instructor’s grades

1.14Questions in solving EX2[3]

Write here your questions, comments, doubts, opinions, etc....

[1]

[2] As you know form EX1A, we have more than 8 different training platforms, which can be used to test your designs.

[3] Add more sheets if necessary to report your progress or comments though the exercise.