0805Prod.doc
******** ANALYSIS & NEWS **************
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Analog IC Prices Under Pressure Amid Weak Demand
According to a recent report from iSuppi Corp., pricing for analog ICs dipped in the first quarter of the year. The cause of the dip was listed as an inventory correction combined with a weak sales start for the year. Price erosion is expected to resurface more vigorously in the second half because seasonal consumer demand during the period is not likely to meet expectations.
The Average Selling Price (ASP) of analog ICs declined by 5 percent in the first quarter of the year and 1.8 percent in the second, according the an iSuppli report by Gary Grandbois. Analog IC ASPs and lead times now have been on the decline for the past two quarters. Although overall analog lead times have contracted substantially since the end of 2004, they have bounced around as the expectation of easy availability of parts has boosted short-term ordering and temporarily extended lead times on specialty products.
Application-specific analog ICs, which constitute two-thirds of the analog IC market, took the biggest pricing hit in the first half of 2005. However, these devices are subject to a distinct seasonality in demand, which invariably spurs an ASP decline in the first quarter.
Despite some positive signs, the analog IC market is not showing much strength compared to 2004. The better-than-expected demand for PCs and mobile phones in the first half has blunted the seasonal slowdown. However, despite the good news, the outlook does not bode well for pricing in the second half of 2005.Price erosion is expected to resurface more vigorously in the second half because seasonal consumer demand during the period is not likely to meet expectations. High energy costs are starting to impact the market and this will generate sluggish growth and significant price pressure through the first half of 2006. iSuppli does not expect that analog IC prices will generally rise until late 2006.
The iSuppli report concluded with a prediction that the analog IC ASP will suffer another 3.1 percent decrease in the third quarter and a 2.3 percent decline in the fourth. For more information, contact iSuppi Corp. at
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IEEE Council on EDA (CEDA) Elects Officers
The newly formed IEEE Council for Electronic Design Automation (CEDA) concluded its first election of officers last week and named Design Consultant Alfred E. Dunlop its president. Giovanni (Nanni) De Micheli, director of the Integrated Systems Centre at EPF Lausanne in Switzerland, is president elect.Elected to the positions of vice president are: Wayne H. Wolf of PrincetonUniversity, (finance); Andreas Kuehlmann of Cadence Berkeley Labs (technical activities); EDA Consultant Richard C. Smith (conferences); and Rajesh K. Gupta of the University of California at San Diego (publications). A runoff election for the position of secretary will be held within the next month.All will serve two-year terms that end December 31, 2007.
Five IEEE societies are part of CEDA, including: Antennas and Propagation Society; Circuits and Systems Society; Computer Society; Electron Devices Society; and Solid State Circuits Society. More societies are expected to join.To learn more, visit the CEDA website (to be launched in the near future) at:
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SOI Kit at 90 nm -- SOISIC (Santa Clara, CA) just introduced a Customer-Owned-Tooling (COT) design kit for 90-nm Silicon On Insulator (SOI) chips. This design kit will enable fabless semiconductor companies to complete successful designs that are up to 35 percent faster and reduce power consumption by as much as 50 percent compared with chips manufactured on bulk CMOS processes. The company’s design kit is silicon-proven on Freescale Semiconductor’s advanced 90nm SOI process technology.
The design kit consists of multi-Vt standard cell libraries, memory compilers and standard I/Os for manufacturing on Freescale’s 90-nm SOI process technology. The immediate availability of the kit marks the entry of SOI technologies in the mainstream COT market. The kits let SoC designers design with their industry standard EDA tool flows. No specific tools or retraining of customer engineers is required because all SOI specific effects are handled at the IP level making it fully transparent to the designers. To learn more, visit the company website at:
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FPGA and PHY Combined -- Altera Corporation (San Jose, CA) and Texas Instruments Inc. (Dallas, TX) recently announced a partnership to develop a PCI-SIG compliant, low-cost PCI Express solution using Altera’s CycloneTM II FPGAs and the latest generation TI x1 physical layer (PHY) chip. The partnership addresses the need for a programmable, low-cost, fully compliant reference design for embedded systems bridging from legacy interfaces.
The TI and Altera solution allows designers to choose from different flexible TI PHY interfaces connecting to the Cyclone II FPGA. It also addresses emerging embedded PCI Express applications, including PC peripheral cards, video and image processing equipment and networking equipment. Customers can use Cyclone II FPGAs for developing lower-cost high-volume products, such as DVD players, camcorders, displays, TV sets and other consumer electronic devices. TI recently announced its third-generation PCI Express PHY chip targeted at low-cost FPGAs in PC add-in cards, communications, test equipment, servers and other embedded system applications.For more information about Altera’s Cyclone II FPGA family, please visit More information about TI’s PCI Express portfolio can be found at
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Analog Virtual Prototype -- Accelicon Technologies, Inc. (CupertinoCA), has announced the production release of Analog Virtual Prototyping (AVP). Several major mixed-signal and analogsemiconductor companies spent over a year, as development partners, working with Accelicon to define, develop and test AVP. The company demonstrated a pre-release version of AVP at DAC 2005 to over 30 analog and mixed-signal semiconductor companies. The AVP circuit designer uses a virtual prototype early in the design process to make decisions about packaging, cost and performance. This process provides an early and accurate physical representation of analog circuit. Floorplanning and circuit partitioning are done at this stage, and various analysis such as power, parasitic and packaging can be studied. AVP is fully integrated into the Cadence Virtuoso product suite and accepts a schematic for input. Using Accelicon’s patent pending ‘signal flow driven’ methodology, a complete transistor level floorplan can be generated in minutes, without requiring the user to specify constraints. AVP will supply an analog correct layout automatically. The engineer may make modifications at the floorplanning stage and conduct a what-if analysis between design and floorplan. When satisfied with the floorplan, the user may view the full layout in Virtuoso. AVP also supplies optimum constraints to the Cadence VCR router to complete the design. To learn more, visit the company website at:
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Coprocessor Delivers for Camera – CriticalBlue (San Jose, CA) has announced the successful completion of a digital camera project for STMicroelectronics (Geneva, Switzerland). CriticalBlue’s Cascade was used to automatically offload unmodified embedded software from the main processor and onto an optimized coprocessor architected by Cascade. The coprocessor was run on a Xilinx Virtex-IITM device within a prototype system.
STMicroelectronics’ audio application was ~ 5,000 lines of C code. Analysis of the profiling results of the application indicated that, to free up >90% of the main processor’s execution cycles, over 200 functions would need to be offloaded onto a Cascade coprocessor. Working directly from the compiled executable code of the complete application, the tools produced a series of candidate architectures based on user defined system constraints. Once the best architecture had been identified, Cascade optimized and generated RTL for the coprocessor as well as creating the coprocessor’s microcode. The offloading of the 200 functions was handled entirely by tool, including the necessary hardware and software interfaces between the main processor and the coprocessor. The final stage of the flow was to simulate and verify the RTL and then to use the Synplify Pro software to optimize and map the coprocessor onto a prototype system based on Xilinx Virtex-IITM FPGAs. For more information, visit the companies website at and