CS6710 Final Project Proposal
Group 2: Jinpeng Lv (u0611330), Xianzong Xie (u0592810), KyungJin Park (u0612283), Byong Wu "Bernard" Chong (u0560467)
Date: 2008/11/11
I. Abstract
Clock gated MIPS processor may obtain low power consumption without significant performance degradation. By gating the clock signal applied to MIPS parts, the processor can cut down dynamic power caused by unnecessary state change in registers. In this team project we will present the how much clock gating will cut down power dissipation caused by MIPS processor.
II. Overview of the Chip Application
The goal of this project is to make a power efficient MIPS microprocessor. Specifically, we will apply Cadence compiler'sclock gating feature togate clocks of unused parts for dynamic power and applya few techniqueforleakage power saving.
II.1 Instruction Set: Include ADD, SUB, MUL, AND, OR, XOR, BNE, BEQ, LOAD, STORE for integer and floatpoint.
II.2 Chip Features
The chip will have following features
- Multistage pipeline
- Bypassing between stages
- Floating point unit
(Reference:
III. Approach
III.1 Mix of Verilog and Custom Circuits
Dealing with digital system modern technology issues high frequency with circuit accumulation this boosts the high temperature. Each new technology is introuduced with limits on frequency and heat problem. To solve this problem we treat clock using mix of Verilog and cumtom circuits. We also tested the cell in formal testing process -Adhoc Tests, Corner Case Tests ( from FF to LL), Memory/Cashe Tests.
III.2 Cell Library
We currently have most of the cells in the library, however, we do not have a full adder cell, yet. Probabily a optimized full adder will be handy on our implementation of ALU unit.
IV. Block Diagram
For the sake of simplicity we willonly present block diagrams of MIPS parts where clock gating will be applied.
Figure 4.1: Clock gated register file Figure 4.2: Clock gated data cache
Figure 4.3: Clock gated register bars between stages
V. Estimation of Design Size
VI. External Interface
Number of Pins
How will we be able to communicate with the chip?
(We can only communicate through the I/O pins we've defined)
External components: Memory Controller, I/O controller
VII. Test
Test parts:
Testing will include Self testing, Clock Skew Test, and General Behavior Test directed at verification of processor pipeline and control function. We will also have a comparison test between circuits with and without clock gating, which can tell us how much the power is saved.
V.1 Self testing
Most of the time we will be testing our parts in Unit Testing style, i.e. all the parts, like ALU, controller, and so on, will be tested individually using bottom-to-up way.
V.2 Clock Skew Test
Since we are making masks to the clock signals, we need rigorous testing of clock skew.
V.3 General Behavior Test
The microprocessor will be tested with several benchmarks and micro assembly programs.
V.4 Comparison Test
Since our main feature is to make the MIPS processor power-efficient, we can have test to determine whether the clock gating works and what is the speedup of clock gating.
VIII. Estimated Tasks