Discussion of EMI of ASIC/3 Product in Development

Discussion of EMI of ASIC/3 Product in Development

Discussion of EMI of ASIC/3 Product in Development /
Alternative Approaches /
Because of the unacceptably high EMI determined during early testing of the ASIC/3 PCB as currently designed, some alternative approaches to solving this problem are discussed. /
Don M. Evans /
9/2/2011 /

During the course of discussions with ASI Controls engineering staff, Paul Chapman and Kosta Economides, the problem of satisfying the Federal Communications Commission (FCC) requirements for maximum Electro-Magnetic Interference (EMI) was considered. The problem seems to exist when and only when the Ethernet cable is installed as a necessary attribute of the normal operation of the ASIC/3. Early testing by an independent testing facility has indicated higher than acceptable radiation levels obtained during measurements utilizing standard measurement equipment at a nominal distance of three (3) meters. This early testing indicated levels just under three (3) decibels (db) above acceptable limits.

Further testing at ASI Controls has resulted in identifying radiation coming from and through the ground plane system of the so-called ‘brain board’, a small independent printed circuit board (PCB) containing the microprocessor (uP) and associated memory and memory management hardware elements.

Certain tests have been conducted by the Engineering Staff at ASI Controls, leading to a determination that by lowering the uP clock rate, a comparable lowering of the EMI level is achieved, as would be expected, looking at Maxwell’s Equations. EMI emissions are due principally to the very rapid rise and decline of wave fronts in the uP due to its digital nature. The more rapid the rise times of signals, the higher the harmonic frequency levels found and emitted. One need only refer to Fourier Transforms to validate this expectancy.

One could expect that by lowering the clock rate sufficiently, all EMI emissions would be lowered to well below the Class A FCC limitations. This is one of the available options to solve the current problem. This approach is quite possibly the easiest to implement, however, future manifestations of the controller may well depend heavily upon high speed of response beyond what a lowering clock rate would countenance.

A second option that would normally result from this study is to modify the PCB so as to preclude any emission from the ground plane of the PCB. This is certainly possible, but would result in a significant delay in the ultimate completion and release of this new product, the ASIC/3. Certain newly developed techniques could be applied to help reduce the emitted signals.

Unexpectedly, a third option has become apparent. As recently as the past few days or a week, ASI Controls has been notified that the uP currently designed into the ASIC/3 has been placed in the ‘Legacy’ category at the uP manufacturer. From our extensive experience with IC manufacturers over the past dozen or so years, moving a product to the ‘Legacy’ category is tantamount to a public announcement that the product will shortly be abandoned in favor of some new, comparable product. With this new information, ASI Controls Engineering Staff has identified a replacement product that actually exceeds the performance characteristics of the current uP in the ASIC/3, but also consumes significantly less power in doing so. Part of the power reduction is in the lower operating voltage, some eight tenths of a volt less than the current uP. Though this sounds like a small reduction in voltage, it represents over fifty percent lower operating voltage. If resulting currents within the uP remained at their current level, then a linear reduction in power level would be realized. However, typically, currents throughout an

integrated circuit are somewhat reduced with lower operating voltages, but not linearly, so it is difficult to forecast added savings in power consumption due to lower operating currents. Since radiated Power Density (Pd) in radiated signals is proportional to the emitting antenna Power (Pa) and inversely proportional to the area of the expanding spherical volume (4, there will result at the very minimum, an EMI reduction of over fifty percent, probably somewhat more due to lower operating currents in the lower power uP. In engineering terms, this amounts to a decibel reduction. db=10log(P1/P2). If P1/P2 = ½, then the reduction of EMI in db = 10(log)* 0.5 = 3.01029996.

3db reduction in EMI emission appears to be sufficient to drop below the required FCC limits at 180 MHz, where the FCC testing was performed. If the clock rate should be increased above 220 MHz, some increase in EMI emission will result, but there is fortuitously an increase of seven (7) db of the FCC limits at and above that frequency.

It is the recommendation of the author of this report that the Engineering Staff of ASI Controls proceed with a new FCC testing cycle, with the new lower power uP installed and at the frequency at which the Staff feels appropriate for future developments. Back up provisions should be made to lower the clock frequency should tests at the higher frequency prove to be unacceptable or marginal.

The author does not want to indicate that further PCB work should not be undertaken to determine a methodology to minimize EMI emissions from the board, but because of the ‘Legacy’ nature of the new classification of the existing uP in the ASIC/3, it seems most appropriate to prepare for the new replacement uP, rather than spend valuable resources attempting to make the current uP more acceptable.

Those prototypes that are currently available utilizing the original uP can be fully utilized for advanced Quality Assurance studies by operating them at a reduced clock rate, which should not materially affect the functionality of the ASIC/3 controller.

Don M. Evans
Evans Associates
3149 Stanley Blvd.
Lafayette, CA 94549
925 947-5781