Device Design Stage 2: Modified Microchannel Test Design

Device Design Stage 2: Modified Microchannel Test Design

Device Objective:

Based on the design of Stage 1, and the inability to fabricate and test the design because of packaging integration problems, Stage 2 had three major objectives. The first objective was to adapt the reservoir positions from Stage 1 to locations matching the existing acrylic packaging solution. The second objective was to reduce the number of I/O and interconnects to produce unique flow paths to test different flow conditions and routes. Finally, the third objective was to scale up the dimensions of the device to ease fabrication and testing. The overall objective of Stage 2 is to address the shortcoming of Stage 1 to test the viability of a two level passive micro-fluidic device. Fabrication and test data from this stage will be necessary to move toward the eventual goal of a two level actively controlled micro-fluidic device.

Device Logic:

As i Stage 1, the device for Stage 2 was to be constructed by stacking PDMS layers on a silicon wafer. The PDMS layers were to be made from a SU-8 based mold. In Stage 2, this stacking sequence included two distinct micro-channel layers, one interconnect layer, and one top cover layer to provide a seal with the acrylic packaging. Also based on Stage 1, the logic of Stage 2 continues to use a simple grid pattern to move fluid within and between fluid layers. However, the locations of the reservoirs were changed to fit the existing acrylic packaging option to facilitate testing. Moreover, as can be seen in Figure 1 below, the design includes five distinct fluid paths, using a total of 11 I/O.

Figure 1: A diagram of the Stage 2 device

Each of the five fluid paths were chosen to test increasingly more complicated situations, culminating in Fluid path 5, which was to mimic a more realistic fluid path that is more likely to be found in micro-fluidic routing. The five fluid paths test both the logic capabilities of the design as well as the capabilities of the process used to fabricate the device. Table 1, below, outlines the five fluid paths constructed.

Table 1: A Table summarizing the five fluid paths in the Stage 2 device

Fluid Path 1: This path proceeds down from the input reservoir to the bottom microchannel layer, across the wafer, and back up the output reservoir. This fluid path serves to test the ability of the device to handle simple flow through the interconnect layer.

Fluid Path 2: This path proceeds down from the input reservoir to the top microchannel layer where the fluid is directed in two sequential 90 degree turns and returns back to the I/O next to the input reservoir, where it then exits up the output reservoir. The purpose of this path was to test the ability of the device to handle direction of the fluid in more complicated fluid paths.

Fluid Path 3: This path proceeds down from the input reservoir to the top microchannel layer, where the path runs across the top layer, down to the bottom microchannel layer, across the bottom microchannel layer, and finally up the output reservoir. The purpose of this path was to test the ability of the device to handle more complicated fluid flow (as in Fluid Path 2) on two levels.

Fluid Path 4: This path proceeds down from the input reservoir to the bottom microchannel layer, where the path runs across the bottom layer, turns 90 degrees, then proceeds up to the top microchannel layer, across the top microchannel layer, down to the bottom microchannel layer, across the bottom microchannel layer, and finally up the output reservoir. This path is logically similar to Fluid path 3, except an additional 90-degree turn and layer change were added for additional complexity.

Fluid Path 5: This path proceeds down from the input reservoir, across the bottom microchannel layer, up to the top microchannel layer, and diverges in two possible directions, each of which leads to a different output reservoir. The purpose of this path is to test a situation where the fluid has more then one possible fluid path. Moreover, this fluid path is ideal for the testing of a valve in future design stages to direct the flow in one of the two possible directions.

Device Dimensions:

Based on the dimensions of Stage 1, the dimensions of Stage 2 were scaled up to ease in fabrication and testing. Table 2 below summarizes the critical dimensions that were chosen for Stage 2.

Table 2: A table summarizing the critical dimensions of the Stage 2 device

Critical Dimension / Value
PDMS Layer Height / 100m
Microchannel Width / 500m
Interconnect Width / 1000m
Interconnect Depth / 1000m
Reservoir Diameter / 0.4 cm

As in Stage 1, the dimensions were only limited by the maximum PDMS layer thickness of ~100 m and the silicon wafer diameter of 4 inches. Based on these constraints, the dimensions were chosen to make fabrication and testing as easy as possible to observe without the aid of instrumentation such as microscopes, etc. The interconnect dimensions were made twice as large as the microchannel width in case there were problems in aligning the sequential PDMS layers. This larger size interconnect was used to guarantee the two microchannel layers would be connected despite small misalignments during the layer assembly. The reservoir diameter chosen exactly matches that which was needed to fit within the existing acrylic packaging that is available to the group. Adapting the Stage 2 design to the existing package was seen as a way to facilitate a fast and efficient testing setup.

Materials:

The materials that we used for the fabrication of the Stage 2 device are the following (same as in Stage 1): Silicon, PDMS and SU-8. The Silicon wafer is used as a substrate, as it is cheap and convenient for fabrication processes like lithography. PDMS is a soft polymer that has properties like elasticity, conformality, optical transparency, etc. Due to its conformal nature, devices made of PDMS can be integrated with materials like glass and silicon. So both reversible and irreversible sealing is possible. In this stage, we used PDMS to create layers, as standard lithographic processes make fabrication of these layers possible. And when all the layers are stacked on the top of each other, PDMS easily conforms and makes stacking possible. SU-8 is a negative based epoxy photo-resist consisting of 8 epoxy groups. This photo-resist is photosensitive and forms a cross-linking reaction when exposed to light. During developing, the SU-8 coated regions are not removed. SU-8 is spin coated on a Si wafer, and after developing, can be used to create reverse mold patterns of micro channels, reservoirs and interconnects.

Processing Method With Mask Design:

In our preliminary design, the alignment between channels and interconnects was an important issue that was raised. The misalignment between top layer reservoirs and bottom layer reservoirs could have been a problem. Say input 1 causes liquid to flow through output 1 as well as through inputs 2 and 3 in the preliminary design. This causes overflow of liquid in the channels. The Stage 2 device was designed in such way that the top layer had connections with the layer on bottom. Thus, the preliminary design was modified to make connections between the inlet as well as outlet reservoirs consistent with existing package. We designed our modified masks and the modified versions of the masks are given in Figure 2 below.

Modified Masks

Figure 2: A schematic of the modified masks for Stage 2

With this particular design of mask sets, we encountered certain questions. The questions were:

• How many of the nine channel intersections should be used as interconnects between layers (3 or 9)?
• Should the first channel layer be open or closed on the bottom surface (PDMS or Pyrex bottom)?
• Should a top layer channel be used or should the top remain open?
• Should the size of the reservoir throughputs be the same size or smaller than the reservoirs?

Through the use of golf tees and rubber bands, we created a three-dimensional model of the micro-fluidic device that led to further modifications of the design. We modified our mask design by: re-routing the input and output channels, deleting portions of the channels and reservoirs, and removing some interconnects from the previous design. There were nine interconnects in the previous design, but in the new design, we reduced it to four interconnects. The new mask sets are given below in Figure 3 below:

Mask 1: Bottom fluid layer Mask 2: Interconnect layer

Mask 3:Top fluid layer Mask 4: Top Cover layer

Figure 3: A schematic of the re-modified masks for Stage 2

The processing method of the modified design consisted of the following:

1. Begin with four polished Si wafers.
2. Spin SU-8 (negative photoresist) on Si wafer and pre-bake at 95°C.
3. Align wafer with Mask 1 - (Figure 3) and expose SU-8 to ultraviolet light. Post-bake at 95°C.
4. Develop SU-8 in SU-8 developer and unexposed areas are removed. This creates Mold 1 from Mask 1. In the same way, Mold 2 is formed from Mask 2, Mold 3 from Mask 3, and Mold 4 from Mask 4.
5. After creating the molds, spin on the PDMS less than the vertical dimension of SU-8 protrusions.
6. Dip the Si wafer in a sodium dodecyl sulfate (SDS) adhesion barrier and allow it to dry naturally.
7. Mix PDMS (Sylgard 184, Dow-Corning) 10:1 with curing agent.
8. Spin on PDMS.
9. Bake in box furnace for 2 h at 70°C.
10. Spin PDMS Layer 1 on Mold 1 (Bottom Fluid Layer), PDMS Layer 2 on Mold 2 (interconnect layer), PDMS Layer 3 on Mold 3 (Top Fluid layer) and PDMS Layer 4 on Mold 4(Top Cover layer). Make a total of four PDMS layers: two layers from the channel mold (1 & 3), one layer from the interconnect mold, and one layer from top cover mold. Figure 4 shows the PDMS Layers 1, 2, 3 & 4.

PDMS Layer 1: Bottom fluid layer PDMS Layer 2: Interconnect layer

PDMS Layer 3: Top fluid layer PDMS Layer 4: Top order layer

Figure 4: A schematic of the four PDMS layers of Stage 2

1. Delaminate and stack all four PDMS layers in the following order: Layer 1 (bottom fluid layer), Layer 2 (interconnect layer), Layer 3 (top fluid layer) and Layer 4 (top cover layer). The final result of the stacked PDMS layer is shown on Figure 5.

Figure 5: A schematic of the final Stage 2 device.

Stage Summary

Stage two was designed using the concepts from stage one. The new design fit the grid pattern of stage one to the existing packaging and set up flow paths that would test the functionality of both layers individually as well the interconnects and the ability of the fluid to move through them. Because the overall function of the device stayed the same, the materials and the reasoning behind using those materials also remained.

Stage two accomplished the goal of creating a testable two level micro-fluidic device. Moreover, a small amount of control was added to the system through the manipulation of the fluid channels and interconnects. The creation of the new fluid paths made it necessary to use an additional mold in the fabrication step. This addition mold was in effect the only change made to the processing. Because the materials remained the same, the processing steps also did not change significantly.

The functionality of the device was examined during the testing stage. Because the packaging was not available, testing proceeded using a manual approach. Testing showed that our overall design worked, but that there were some issues with the channel material, PDMS, and the flow pressure required. These results, in part, justified our decisions in stage three.

It appears that the limits of the passive system have been reached. The logical next step is to then integrate a form of valve into the channels to enable even more control over the fluid flow. The materials may need to be altered, taking into account the testing problems from stage two. The channel layout should remain as intact as possible to aid in the feasibility of testing the next stage.