Device Design Stage 1: Initial Microchannel Test Design

Device Design Stage 1: Initial Microchannel Test Design

Device Objective:

Once the design requirements and assumptions were finalized, the group determined that testing preliminary designs on the path to a final design was necessary to ensure constant feedback to assess the practicality of design choices. In this path, the testing of the fluidic channels was of primary importance, as the option of including control elements would be mute if the fluid itself was unable to pass through the channels designed. Therefore, the group generated the Initial Microchannel Test Design. The purpose of this device was to allow the group to test the experimental capabilities available to us, as well as establish a base upon which more complicated devices could be modeled. More specifically, the device was designed to test the viability of basic multi-level micro-fluidic devices with the equipment and materials currently available.

Device Logic:

The design that was chosen consisted of the simplest two-channel layer three-dimensional channel geometry that could be constructed, and at the same time test the practicality of multi-level microfluidics. Moreover, the group decided to use sequential layers of PDMS molds to build up the desired structure. These molds were to be stacked on a bare silicon wafer, which would provide rigidity for transport and testing. There were several reasons for this choice, which included the following:

1. The PDMS layers would allow for heightened design flexibility, as the molds could be re-used and the layers created from these molds could be stacked numerous times in several different orientations.
2. The existing knowledge available to the group based on prior experimental tests done on similar processes by students in the department.
3. The known material compatibility between PDMS and many biological agents that could be used in multi-level micro fluidic devices.
4. The equipment and material constraints based on availability, or lack thereof, of potential materials and equipment for other, less common forms of microprocessing.
5. The PDMS and SU8 molding process was known to have a relatively fast turnaround time, and this was critical due to the time constraints on the semester.

Figure 1 below shows a schematic of the proposed design. The colors (blue, green, and yellow) signify voids within the PDMS (white). The design consists of three layers: one interconnect layer, and two microchannel layers. The lower microchannel layer (shown in blue) connects to the interconnect pegs (shown in green), which in turn, connect to the top microchannel layer (shown in yellow). The circles located at the ends of the microchannels are the reservoirs which run from the top to the bottom layer, and provide top down access points to all the microchannels, thus allowing for fluid access to all microchannels to assist in testing. Fluid flow into anyone of the 12 reservoir inputs would allow the fluid to enter the device and test to ensure the fluid was able to stay within the pre-determined microchannels that were constructed, as opposed to forcing between the layers and resulting in layer delamination.

Micro-Channel Layer 1

Micro-Channel Layer2

Interconnect Layer

Figure 1. A Schematic of the Initial Microchannel Test Design (Top View).

Device Dimensions:

Based on the logic of the design, the group then determined some appropriate dimensions. Given that this was the first design stage of the semester, there were only a few constraints on the dimensions that could be chosen, so the dimensions were chosen based on the approximate sizes encountered in most of the literature. The only constraints that were considered during the device dimensioning were the overall silicon wafer size of Diameter = 4 inches and the fact that the PDMS layers could not be molded to a thickness greater then approximately 100m, given past experimental use with the material. Below in Table 1 is a summary of all the critical dimensions that were determined for this Initial Microchannel Test Design. These dimensions were chosen very loosely as the purpose of this design was to test the general performance of the design proposal and not the specifics of the device geometry.

Table 1. A Table of the critical dimensions for the Initial Microchannel Test Design.

Critical Dimension / Value
PDMS Layer Height / 100m
Microchannel Width / 150m
Microchannel Length / 45mm
Interconnect Width / 150m
Interconnect Depth / 150m
Reservoir Diameter / 300m
Distance Between Channels / 300m

The cross sections of the microchannels were process limited, as the SU8 and PDMS molding process does not easily allow for the creation of ridges or grooves that are non-rectangular. Therefore, the cross-section the microchannels were made rectangular. Given the different orientation of the reservoirs and interconnects relative to the micro channels, they could have been made any number of shapes, however, for simplicity, the interconnects were made square in cross-section and the reservoirs were made circular in cross-section. These dimensions and geometry constituted, what the group thought as, the most basic design option to test the viability of multi-level micro-fluidic devices .

Materials

In the introductory sections, we gave a list of materials that are candidates for this project and an overview of their electrical and mechanical properties. In this section, we will be discussing the materials that are used, as well as why they are used.

At this stage, the materials used for fabrication of our device are silicon, SU-8 and PDMS (polydimethyl siloxane). We selected a silicon wafer as our substrate because it is cheap and convenient for most of the fabrication processes like lithography. PDMS is a soft polymer that has attractive physical properties, in addition to a low cost. Fabricating PDMS involves a lithographic process. It’s physical properties include elasticity, conformality, optical transparency, etc. Devices made of PDMS can be integrated with other components, since PDMS conforms to materials like silicon or glass easily. This conformal property makes both reversible and irreversible sealing possible. It is non-toxic to biological agents, such as proteins, and it is gas permeable. Also, since it is transparent in the visible/UV region, it is compatible with many optical detection methods.

SU-8 is a negative based epoxy photo-resist consisting of 8 epoxy groups. This photo-resist is photosensitive and forms a cross-linking reaction when exposed to light. During developing, the SU-8 coated regions are not removed. The characteristics of this particular photoresist are the following: provides good adhesion to where it is spin-coated, near UV-sensitive, high aspect ratios (~15 for lines and 10 for trenches), and it works for a range of thicknesses (750 nm to 500 m can be coated using a conventional spin-coater). SU-8 is spin coated on a Si wafer, and after developing, can be used to create reverse mold patterns of micro channels, reservoirs and interconnects.

Processing Method with Mask Design

Based on the initial mask design, the process requires the creation of SU-8 molds, which in turn will be used as a template for the subsequent PDMS layers. In this section, the process sequence for the initial design is discussed in detail. The initial mask design is shown in Figure 2.

Mask 1 Mask 2

Figure 2. Mask 1(Channel mask) & Mask 2(Interconnect mask)

Our process sequence begins by coating SU-8 on a Si wafer, exposure using Mask 1 or Mask 2 to create the molds, followed by spinning PDMS on the molds, and finally stacking the PDMS layers to form the final structure. The process sequence is given below:

1)Begin with a polished Si wafer.

2)Spin SU-8 (negative photoresist) on Si wafer and pre-bake at 95°C.

3)Align wafer with Mask 1 (Figure 1) and expose SU-8 to ultraviolet light. Post-bake at 95°C.

4)Develop SU-8 in SU-8 developer and unexposed areas are removed. This creates

Mold 1 from Mask 1. In the same way, Mold 2 is formed from Mask 2. Figure 3

shows both Mold 1 and Mold 2.

Mold 1 Mold 2

SU-8 Protrusions

Figure 3. Mold 1and 2 from exposure and development of an SU-8 surface using Mask 1 and Mask 2 respectively.

5)After creating the molds, spin on the PDMS less than the vertical dimension of the SU-8 protrusions.

• Dip the Si wafer in a sodium dodecyl sulfate(SDS) adhesion barrier and allow it to dry naturally.
• Mix PDMS (Sylgard 184, Dow-Corning) 10:1 with curing agent.
• Spin on PDMS.
• Bake in box furnace for 2 h at 70°C.

6)Spin PDMS Layer 1 on Mold 1 (Bottom Fluid Layer), PDMS Layer 2 on Mold 2 (interconnect layer) and PDMS Layer 3 on Mold 1 at 90° rotated relative to PDMS Layer 1(Top Fluid layer). Make a total of two layers from the channel mold and one layer from the interconnect mold. Figure 4 shows the PDMS Layers 1, 2 and 3.

PDMS Layer 1 (from Mold 1) PDMS Layer 2(from Mold 2)

PDMS Layer 3 (from Mold 1) rotated 90° relative to Mold 1

Figure 4. Three completed PDMS Layers.

7)Stack all three PDMS layers in the following order: channel, interconnect, channel (90° rotation from the first channel layer). The final result of the stacked PDMS Layers is shown in Figure 5.

Bottom layer

Middle layer

Top layer

Figure 5. The final result of three PDMS layers stacked on one another (Top View).

Conclusion

Stage one was designed to be a logically simple device that met the overall objectives of the project. The general concept of how the fluid should flow through the device and between layers appears to be accepted as a viable approach. The materials and the processing of the device also appear to be on target. For this beginning stage, it seems that the fluid flow, dimensions and arrangement of the channels will need to be modified before continuing on to the next stage.

It was determined that adjusting the design to fit the existing packaging would be advantageous for testing. This translates to moving the inlet and out let reservoir holes to the same positions as the inlets and outlets on the packaging. The packaging also has some affect on the reservoir dimensions. The reservoir diameters will also need to be consistent with the diameters of the inlet and outlets on the packaging.

Other dimensions, not affected by the packaging may also want to be changed. For a preliminary design and testing phase ease is of great importance. The dimensions will need to be adjusted so that both ease of manufacturing and ease of testing are optimized.

Lastly it appears that the simple grid design will need to be modified in order to more efficiently test the capabilities of the device. This may include deleting portions of the channels and possibly removing some interconnects.