Design/Verification Issues in Wireless Apps

FPGA Developer – draft 6/1/2006 10

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FPGA Developer

June 6, 2006

Design/Verification Issues in Wireless Apps

www.chipdesignmag.com/fpgadeveloper

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Welcome to the June 2006 edition of FPGA Developer. We complement Chip Design magazine by providing the latest FPGA and Structured ASIC news, opinions from industry experts, and timely technology articles. See below for subscribe and unsubscribe options.

This Month's Table of Contents:

1. Editor’s Note – What Price Success? or "Feed Me, Seymour!"

2. Quality of Results is Everything for FPGA Designs – or is it?

3. Down to the Wire (and Wireless): Is Structured ASIC poised to be or not to be?

4. World's Highest Performance Platform FPGAs

5. Machine Vision Library Offered for FPGA Alternative

6. Open ESL Synthesis Extensions to SystemC Create Unified Environment for Modeling, Design, Verification

7. Expanded IP Portfolio for Military, Aerospace and Communications Applications

8. Combined Offering Key to Rapid, IEEE 802.16e-2005 Wireless Modem Development

9. Next Generation Devices Target Real-Time Data Recording and Image Processing Applications

10. In-Depth Coverage Links

ESL Lives Up to Its Early Promise in Embedded Systems Design

There's No Prize for Taking the Long Road

11. New Book

Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems

12. Happenings

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1. Editor’s Note

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What Price Success? or "Feed Me, Seymour!"

By Jim Kobylecky, Editor

It's not the nineties reborn, but high tech is growing and FPGAs and Structured ASICs are part of it. But where's the growth coming from? Once upon a time, we required wars or enlightened princes to speedup technological research and innovation. This time, however, the primary driver seems to be the trendy taste of a few billion consumers. I'd like to think its rising functionality that explains why people repeatedly buy the wireless device of the month. I'm also waiting for the Cubs to win the World Series. But if we're actually riding a wave of techno-hype, what is our role in feeding the fashion frenzy?

Engineering does not take place in a vacuum (usually). Engineering has a social context. Engineers have social needs. Our actions have social consequences.

Okay, so I'm a fossil. I can recall dim, forgotten days when "planned obsolescence" seemed a horrifying idea. Days when we worried about the outcome of progress and the "Soylent Green is people!" line seemed somewhat shocking. (If you don't know what I'm talking about, ask your parents. If they don't know, ask their parents. If they can't remember, [sigh], try Wikipedia.)

On the other hand, I'll admit that these rapid changes in consumer demand are a big factor in feeding and clothing my family. The same accelerating product turns and shrinking market windows that are driving us nuts are also paying down our mortgages and sending our kids to school. The public's thirst for innovation, whatever the reason, is what keeps Moore's law meaningful. It demands all we can supply. This need engine pushes the development of systems and design tools (and web newsletters) just as hard as it is pushes the world's VISA balances.

But what do I see when the lights go out?

When I was a kid, engineering looked like a ticket out of the dead-end jobs I saw around me. Engineers seemed to be heroes in rolled-up sleeves; they made practical what the scientists (my second choice) kept discovering. I imagined engineers as enlightened beings who worked to make life better. It didn't take long, however, before I realized that someone had to pay me before I could do many great things, and the things they were willing to pay for were only what government or marketplace wanted.

"The Little Shop of Horrors," Roger Corman's classic 1960 B-movie, is the cautionary tale of Seymour, a rather nerdy, well-meaning guy, who can't succeed at anything – until he teams up with a little green plant. Nurturing that plant brings Seymour all the success he'd longed for, but at a price: its asocial appetite. Feeding it (and staying successful) requires Seymour to make increasingly bad decisions at ever higher cost. You can guess the ending. The later stage play adaptation (and the original ending of Frank Oz's 1986 remake) carried the thought even further. Spoiler follows: The plant wins, dispenses with Seymour, and takes over the earth. But viewers were so shocked by that logical conclusion that Oz's film had to tack on a happier ending before it could be released.

By eerie coincidence, the original version also forecast future design requirements and market windows. It was the fastest movie ever shot. Legend has it that it was written in a single night at a 24-hour coffee house. It reused ideas, actors and a set scheduled to be torn down as its IP. Front-end design (rehearsals) took just three days. Place and route (the actual shooting) covered two days. Final programming and verification (editing) took just a few more. Product requirements to tapeout in a little over a week – not bad for 1960.

But before I ponder myself right off the soapbox, let's put things back in perspective. Living off electronic fashion does make me queasy in the macro sense, but in a micro view I love the opportunities and challenges. Technology rocks. I don't exactly long for wars and princes either. They were hardly benign engines of technological growth. The speed-ups brought by armed conflict, whether putting us in space, preserving foods, tempering steel, or cleansing wounds, were made at great cost in human suffering. And the princes had more than science on their minds. Their success and the success of their state (or company) derived from conflicts of trade and political influence (greasing the skids for new wars and conflicts).

So what is under our control? I know I have still have the same dreams and feel the same responsibilities I did at six – that I should use my abilities to build a better world. Some of us will be lucky enough to do it at our jobs. Some of us will have to look for ways to contribute: building houses in Honduras, working on third-world PCs, or programming VCR's for senior citizens. We can't let the plants win without a fight.

One way to start saving the world, is with this issue's Viewpoints. Juergen Jaeger sharpens the discussion on Quality of Results, while Zvi Or-bach looks at Wireless and sees a cautionary tale for Structured ASICs. And then consider our news briefs and other features. We pick them for a reason. Good ammunition for doing the right thing.

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2. Viewpoint – Exclusive

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Editor's Note: This is the second of a three-part mini-series on crucial FPGA development topics.

Quality of Results is Everything for FPGA Designs – or is it?

By Juergen Jaeger, Director of Channel Marketing, DCS Division, Mentor Graphics Corporation (www.mentor.com)

For FPGAs, Quality of Results or QoR — most often meaning the maximum frequency, or fmax, at which a given design runs in a specific FPGA — is probably the most used and abused term when it comes to selecting either an FPGA or FPGA design tools.

No doubt, achieving the desired target frequency is the basic requirement for every FPGA design, but the key word is achieving. Putting extra effort into overachieving the desired target is wasting both time and effort. Although it is important to determine and understand the best QoR possible for a given FPGA design using an FPGA synthesis tool, it is even more important to understand how the various synthesis tools achieve those QoR numbers:

- Are the results applicable to other FPGA families or other vendors?

- Are they repeatable and predictable?

- How much effort was required to achieve the results?

- Does the tool identify the design bottlenecks?

- Does the tool identify why timing is not being met and how to fix it?

Clearly, the question is how easily and predictably can the desired QoR be achieved.

So how can and do today’s advanced FPGA synthesis tools, such as Mentor Graphics Precision® synthesis, help the designer to quickly and repeatedly meet his design goals? As with so many things in life, the answer is, no, not “42” (in homage to The Hitchhiker's Guide to the Galaxy), but “it depends!” For one, it depends on the use-model (FPGA for production, or FPGA for ASIC prototyping) as well as on what the other major design requirements are.

Let’s talk first about the use of FPGAs to prototype ASIC functionality. Although ASIC prototyping typically does not generate much FPGA revenue, mitigating the risk of expensive ASIC re-spins represents tremendous value and ROI potential for companies. Even though QoR for ASIC prototyping matters somewhat, it is not the primary goal. However, what is important is that the tool can easily map all or part of an ASIC design into an FPGA, thereby preserving the correct functionality. More important than raw QoR are capabilities such as adherence to standards for design constraints and language, incremental design capabilities for fast turn-around, comprehensive design visibility/analysis capabilities, and of course, the ability to automatically map ASIC design constructs, such as gated clocks, memories, etc. into an FPGA architecture.

If the completed FPGA design will end up as part of an end product, then the requirements are somewhat different — achieving the desired QoR is the key requirement, but it’s only one milestone in the quest for success.

More often than not, the first design run does not achieve the desired performance, resulting in the question of why and how can it be fixed? So in this phase, the most important set of capabilities the design tool has to provide are comprehensive timing and design analysis. Early discovery of throughput issues requires completing a more in-depth analysis of performance and timing issues throughout the synthesis process. Similarly, before cycles are spent trying to meet the timing constraints in place and route, are the constraints even complete? Early discovery of timing issues requires analysis of constraint coverage during synthesis.

Interactive synthesis techniques provide more predictability in the design flow. An indispensable weapon in any FPGA designer’s toolkit is a capable, interactive synthesis and analysis environment that goes all the way from RTL to physical implementation. Interactive synthesis techniques provide guidance to the designer, allowing “what-if” explorations earlier in the design cycle. A sophisticated synthesis environment also provides a variety of design representations: as high-level operators, architecture-specific technology cells, etc. Taking advantage of these capabilities provides an earlier understanding of the nature of the design and whether it will (or perhaps will not) meet specifications.

Vendor-independence is not mutually exclusive to QoR. Vendor-independent flows increase productivity and enable design reuse. A consistent vendor-independent synthesis and verification flow allows for the exploration of the capabilities offered by each of the various FPGA architectures within a single environment. This approach reduces the need to learn device-specific coding techniques and attributes just to complete an architecture evaluation. It also eliminates the training overhead associated with having to learn multiple design environments.

To help designers meet their specifications, today’s programmable logic synthesis tools have raised the bar significantly over their predecessors in the level of sophistication exhibited by their high-level operator extraction and mapping. Recent technological advancements have provided intelligent multi-vendor device support, with inferencing and mapping to on-chip dedicated resources like DSP hardware and RAM. Making the most of these technology advancements in synthesis also reduces vendor-dependent design content, thus easing migration and maintenance efforts.

While FPGA vendors have equated QoR solely with fmax, how tools help designers meet this requirement is as equally important. Achieving a successful FPGA design is more than just hitting a number, it is a process.

Comments about this article? Share your thoughts by writing our editorial director: .

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3. Viewpoint – Exclusive

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Down to the Wire (and Wireless): Is Structured ASIC poised to be or not to be?

By Zvi Or-bach, eASIC Chairman & CTO (www.eASIC.com)

In today’s marketplace, driven significantly by digital consumer products, wireless connectivity promises a huge opportunity for diverse markets with a wide range of new applications. Mobile computing, home and factory automation, and broadband connections are all targeted with new, fast-changing standards. Amid this hectic market environment, we experience a growing trend of product commoditization. For example, the mobile infrastructure industry is facing new major challenges as standardization turns base stations into commodity products. Evidently, innovation and product differentiation are now more than ever vital for sustaining healthy company growth. The search for an affordable IC solution for customized-differentiated applications led many electronics designers to investigate the newly introduced solution called Structured ASIC. The Structured ASIC was described by industry analysts as “The preferred design solution for the future”, which is “proving to be highly promising components for next-generation devices …solving cost and design issues in the IC industry”.

But recently, one of the major Structured ASIC players, LSI Logic, ceased further development of its RapidChip, and Synplicity made a similar follow-on announcement. This raises an inevitable question: is Structured ASIC just a “bubble solution” or is it a real breakthrough that is here to stay?

First, we need to clarify the term Structured ASIC, which seems to be confused with the short-lived phrase ‘Structured Array’ introduced by LSI Logic in the 90’s. I support the definition that Structured ASIC should apply to all of the ASIC solutions that require some custom masks/layers but far less than the solutions requiring full mask-set used for Standard Cell ASIC.

It is notable that the Gate Array, which dominated the ASIC technology in the pervious two decades, meets this definition as well. In fact, this Structured ASIC description fits perfectly the RapidChip product. Some people believe erroneously that FPGA killed the Gate Array business, but the reality is that the submicron IC technology, advancing below 0.35 micron, caused the Gate Array value proposition to dissolve. Once the metal layers started dominating the chip delay, affecting the masks cost and the manufacturing time, there was no longer a compelling value in compromising on die size and fixed transistors structure.