TEXAS A&M UNIVERSITY
Department of Electrical and Computer Engineering
College Station, Texas 77843-3128
TEL (409) 845-7498 FAX (409) 845-7161
http://amesp02.tamu.edu
S E M I N A R
Room 227A ZEC
Thursday, November 1, 2007 3:55 - 5:10 P.M.
Design Challenges for Mixed-Signal Nanometer CMOS Single-Chip Broadcast Receiver SOCs
by
Adrian Maxim,
Silicon Laboratories, Austin TX
Abstract: In spite of the large volumes enjoyed by the broadcast receivers (TV + radio receivers match the cellular transceiver volumes), they are largely dominated by low level integration solutions, having a large number of off-chip components. The main rational of using discrete solutions for the RF front-ends is the stringent noise figure (NF=5 to 6dB) in presence of strong blocker channels and high linearity requirements (IIP3=+20 to +25dBm) that need to be ensured for a very wide frequency range. Coping with the large undesired-to-desired channel power ratios (up to 60dB) mandates either high selectivity filters that track the desired channel frequency (high order passive LC networks), or very high linearity in the signal path up to few GHz. Today’s boom in digital TV and digital radio renewed the efforts to integrate the entire broadcast receiver in a single-chip or a single-package solution. If the integration was successful for the more relaxed cable (Open-cable / DVB-C) and satellite (DVB-S) standards, for the mobile (DVB-H) and terrestrial (ATSC / DVB-T) standards, the silicon tuners are still struggling to get accepted.
Since cost and performance are the key design targets and power / board area are only secondary concerns, the non-portable broadcast receivers have moved on a different integration path, when compared with their cellular transceiver counterparts. The aim of this talk is to present the main challenges faced by single-chip / single-package broadcast receiver integration, analyze the existing discrete and silicon tuner architectures, investigate the available processes and assembly methods (SoC, SiP) and present today’s and tomorrow’s trends in broadcast receiver integration.
Integrating both the RF front-end and the digital back-end of a modern receiver on the same die raises multi-disciplinary challenges: technology, device modeling, circuit design, circuit and system level simulation, layout and packaging. This talk presents both basic and advanced design techniques that allow the realization of a high performance RF front-end, while operating on the same substrate with a large and noisy digital core.
Another challenge for mixed-signal receiver SOC integration is designing the frequency synthesizers, which require a very low sensitivity to substrate and supply noise coupling.Both magnetic and electric parasitic couplings need to be minimized. Multi-regulator architectures and high PSRR/low supply pushing circuit techniques are investigated for low phase noise and low spur PLLs. Ring oscillators are better suited for DVB-S and DVB-C applications, while LC oscillators are more appropriate for DVB-T and DVB-
TEXAS A&M UNIVERSITY
Department of Electrical and Computer Engineering
College Station, Texas 77843-3128
TEL (409) 845-7498 FAX (409) 845-7161
http://amesp02.tamu.edu
H tuners. The main spur coupling mechanisms are investigated for PLLs operating in a large SOC environment and circuit techniques are proposed for their rejection.
Content:
· Broadcast receiver specifications
· Available silicon processes and assembly technologies
· System partitioning and integration for cost and performance
o tuner – demodulator - MPEG host processor - controller
· Integration issues with existing silicon tuner architectures
o Dual and single conversion receivers
o Up-down dual-conversion receivers
o Zero-IF and Low-IF receivers
o SAW-less Digital low-IF receivers (digital-SAW architecture)
· Image and harmonic rejection mixers that compensate for the lower selectivity of the integrated tracking filters
· Frequency synthesizer architectures for broadcast receiver SoCs
· SoC versus SiP for broadcast receivers
· Future directions in broadcast receiver integration
o Multi-tuner SoCs
o Reconfigurable receivers
o DSP assisted receivers
o Software defined and software assisted receivers
· Conclusions
Dr. Adrian Maxim was born in Iasi, Romania in 1968. He received the B.S.E.E. degree (with honors) in 1992 and the M.S.E.E. degree in 1994 from the Technical University of Iasi, Romania. He received the Ph.D. degree (1998) from the Technical University of Iasi, Romania and the National Polytechnic Institute of Toulouse, France for his work on SPICE macromodeling of semiconductor devices. He has received the Leopold Escande award for outstanding Ph.D in electrical engineering from the National Polytechnic Institute of Toulouse, France. Dr. Maxim was an Assistant Professor (1994-1998) and then an Associate Professor (1998-2001) at the Technical University of Iasi, Romania, Department of Electronics and Telecommunications, where he was involved in research on power semiconductor devices physics and modeling and advanced architectures for multi-GHz frequency synthesizers. During 1998 he was an Invited Professor at the National Polytechnic Institute of Toulouse, France. From 1998 to 2001 he consulted with Crystal Semiconductor Division of Cirrus Logic, Austin TX and worked on multi-GHz frequency synthesizers for large mixed analog-digital SoCs. From 2001 to 2004 he was with Maxim Integrated Products as a Senior Member of Technical Staff in the Fiber Optic Division, designing ICs for 10Gbps optical links and clocking applications. Dr. Maxim is now with Silicon Laboratories, Austin TX as a Senior RF Architect working on RF tuners and wireless transceivers. His research interests are in advanced PLL synthesizer and RF front-end architectures for wireless and wireline applications. He authored three books on SPICE modeling of semiconductor devices and circuits and over 60 technical papers in IEEE Journals and Conferences. Dr. Maxim is serving as a Technical Program Committee member for the IEEE International Solid-State Circuits Conference (ISSCC) and the IEEE VLSI Symposium.