Introduction to 80x86Data Transfer Instructions

Instruction Cycle

There are three operations performed by the CPU in the execution of one instruction:

Fetch / The control unit fetches the instruction, copying it from memory into the instruction queue, and increments the program counter
Decode / The control unit determines the type of instruction to be executed. If a memory operand is needed, the control unit initiates a read operation to retrieve the operand. It passes zero or more operands to the arithmetic logic unit (ALU) and sends signals to the ALU that indicate the type of operation to be performed
Execute / The arithmetic logic unit executes the instruction, returns its output into the destination operand, and updates status flags providing information about the output

An important feature of today's microprocessors is their division of labor between the arithmetic logic unit and the control unit allowing them to work in parallel. Rather than wait for the arithmetic logic unit to finish each instruction, the control unit fetches the next instruction from memory and loads it into the instruction queue.

80x86 INSTRUCTION TYPES

The instruction set of the 80x86 microprocessor may be divided into seven different groups:

Data Transfer / The data transfer group contains instructions that transfer data from memory to register, register to register, and register to memory. Instructions that perform I/O are also included in this group. Data may be 8-, 16-, or 32-bits in length, and all of the registers may be used (including the stack pointer and flag register).
Arithmetic / The arithmetic group provides addition and subtraction of 8and 16-bit values, signed and unsigned multiplication and division of 8-, 16-, and 32-bit numbers, and special instructions for working with BCD and ASCII data.
Bit Manipulation / The bit manipulation group is used to perform AND, OR, XOR (Exclusive OR), and NOT (1 's complement) operations on the data contained in registers or memory. Shift and rotate operations on bytes and words are also included, with single or multi-bit shifts or rotates possible.
Strings / A string is simply a collection of bytes stored sequentially in memory, whose length can be up to 64KB. Instructions are included in this group to move, scan, and compare strings.
Loops and Jumps / Many different forms of instructions are available, with each one testing a different condition based on the state of the processor's flags. The loop instructions are designed to repeat automatically, terminating when certain conditions are met.
Subroutine and Interrupt / The subroutine and interrupt group contains instructions required to Call and Return from subroutines and handle interrupts. A special form of the return instruction can manipulate the processor stack, and two classes of subroutines, called near and far procedures, are handled by these instructions.
Processor Control / The final group of instructions is used to directly control the state of some of the flags, enable/disable the interrupt mechanism, and synchronize the processor with external peripherals (such as a coprocessor).

Many different addressing modes can be used with most instructions, and in the next section we will examine these addressing modes in detail.

Data Transfer Instructions

The MOV instruction transfers the content of the source operand to the destination operand

mov destination, source

The MOV instruction requires that both operands must be the same size. The operand can be either direct or indirect.

Direct operands

immediate (imm) (may be a constant or constant expression)

register (reg)

memory variable (mem) (with displacement)

Indirect operands are used for indirect addressing (this will be covered later in Addressing Modes)

Note. The following instructions in italics are illegal and will cause the assembler to generate error messages. Instructions that are not in italics are correct syntax.

Some restrictions on MOV

imm cannot be the destination operand...

IP cannot be an operand

the source operand cannot be imm when the destination is a segment register (segreg)

mov ds, @data ; illegal

The previous instruction was an attempt to load the DS (Data Segment) register with the address of the data segment. This can and should be done. However, it requires two instructions. These instructions should be the first two instruction in our programs and would be as follows:

mov ax, @data ; legal

mov ds, ax ; legal

The source and destination operands cannot both be memory

mov wordVar1,wordVar2; illegal

The type of an operand is given by its size (byte, word, doubleword, quadword)

both operands of MOV must be of the same type

type checking is done by the assembler

the type assigned to a memory operand is given by the programmer when he/she uses the data allocation directive (DB, DW…)

the data type assigned to a register is given by its size (8-bit, 16-bit, etc)

an imm source operand of MOV must fit into the size of the destination operand

Examples of MOV usage

mov bh, 255; 8-bit operands

mov al, 256; error: source operand too large

mov bx, AwordVar; 16-bit operands

mov bx, AbyteVar; error: size mismatch

mov edx, AdoublewordVar; 32-bit operands

mov cx, bl; error: operands are not the same size

mov wordVar1, wordVar2; error: memory-to-memory

We can add a displacement (offset from the base address) to a memory operand to access a memory value

Example:

.data

arrB db 10h, 20h

arrW dw 1234h, 5678h

For the data declarations above, arrB+1 refers to the location one byte after the base address of arrB and arrW+2 refers to the location two bytes after the base address of arrW.

mov al,arrB ; AL <= 10h

mov al,arrB+1 ; AL <= 20h (memory with displacement)

mov ax,arrW+2 ; AX <= 5678h

If you cannot see the previous instruction, the address is +2 bytes. That is why we are loading the second word of the data storage. If we had used:

mov ax,arrW+1 ; AX <= 3456h

AX does not receive the proper word-boundary value so do not fall into that trap. However, this might be a logical error and may cause an error at run time. We will not be warned.

The XCHG instruction exchanges the contents of the source and destination operands. The format of the instruction is:

XCHG destination, source

Only memory and reg operands are permitted (and must be of the same size). Both operands cannot be memory (direct memory-to-memory exchange is not supported in the Intel processors). To exchange the content of word1 and word2, we have to do:

mov ax,word1;AX <= word1

xchg word2,ax;word2 <= AX

mov word1,ax;word1 <= AX

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