1/15/2008
COMP326/526 Section DD Tutorial #1
Announcements:
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select COMP326-w08
Other students are welcome and encouraged to give their response or additions to a topic. If you send an e-mail to me personally and I deem it to be worthwhile to the whole class, I will remove the poster’s name to preserve anonymity.
- Tutorial WEBsite: http://www.cs.concordia.ca/~hotpoint/comp326/
- The transcripts of the lectures and tutorials will be posted if and whenever time permits.
- The tutorial times will be as follows:
20:15 – 20:35 Short break and assignment logistics
hand in assignments at the beginning of the tutorial,
or pick up any marked assignments. Late submissions
should be requested beforehand.
Also, simple questions can be dealt with here.
20:35 ~ 21:30 Interactive lecture
21:30 – 22:00 Q & A, office time. When everybody has gone, I leave to.
- Online Q & A can be anytime, I will answer when I have the time and/or once I have researched for a good answer. Face-to-face office hours are discouraged.
An overview of topics that will be covered during the term follows on the next pages.
Amdahl’s law - benchmarks and performance metrics.
E = (A*B) + (C*D)
LD r1,A
LD r2, B
MUL r2,r2,r1
ST r2,F
LD r1,C
LD r2,D
MUL r2,r2,r1
LD r1,F
ADD r1,r1,r2
ST r1,E
loop
- in software, one could use more registers to avoid having bubbles.
How to measure the performance of a machine.
MIPS
CPI
CPU Time
SPEEDUP (Amdahl’s Law)
Baby Pipelining.
- present block diagram and compare to the computer block diagram of COMP228.
- mention the five stages that our simple example computer will use: FDXMW
- discuss pipelining instructions and some relationships between instructions and how this can be problematic.
- timing diagrams
- bubbles/hazards.
- longer stages such as floating point multiply and divide and memory accesses make it worse.
Advanced Pipelining Techniques.
- ILP – Instruction Level Parallelism
- loop unrolling.
- Software pipelining.
- long instruction word.
- multiple issue of instructions.
- scoreboard
- Tomasulo’s algorithm – register renaming.
- - out of order execution.
- caching.
- pre-fetch.
- store buffer.
- quad word transfer.
- branch prediction.
I may bring out an extra presentation about the Pentium 4, Netburst Architecture and Hyperthreading some time after these topics have been covered.
Memory Organization.
- addressing.
-
- interleaving.
-
- cache.
Shared Memory in Multi-processors.
Vector Processors.
- SIMD
I may present some information about MMX and Video pipelining and how they do multiple data processing like the vector processors are designed to do.
Interconnection Networks.
- A lot of similarities to stuff covered in the networks course; COMP445.
- I may also present an idea for the future that may manifest.
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