Award Software
Chipset Features Setup
This section allows you to configure the system based on the specific features of the installed chipset. This chipset manages bus speeds and access to system memory resources, such as DRAM and the external cache. It also coordinates communications between the conventional ISA bus and the PCI bus.
Auto Configuration
By enabling the Auto Configuration, you will not need to individually configure various settings. This returns your system configuration to the highly optimized (and recommended) state it was delivered in.
DRAM Read Wait States
This sets the number of wait states used while reading DRAM.
0 WS / Zero wait states for DRAM write1 WS / One wait state
2 WS / Two wait states (Default)
3 WS / Three wait states
DRAM Write Wait States
This sets the number of wait states used while writing to DRAM.
0 WS / Zero wait states for DRAM write (Default)1 WS / One wait state
2 WS / Two wait states
3 WS / Three wait states
L1 Cache Update Scheme
This allows you to set the write policy for the CPU’s internal cache. The options for this feature are Write-Back and Write-Through. Write-Through means that memory is updated with data held in the cache whenever the CPU issues a write cycle. On the other hand, Write-Back causes memory to be updated only under certain conditions such as read requests to the memory whose contents are currently in the cache. Write-Back allows the CPU to operate with fewer interruptions, increasing its efficiency.
Wr-Back / Write Back enabledWr-Thru / Write Through enabled
L2 Cache Update Scheme
This allows you to set the write policy for the CPU’s external cache. The options for this feature are Write-Back and Write-Through. Write-Through means that memory is updated with data held in the cache whenever the CPU issues a write cycle. On the other hand, Write-Back causes memory to be updated only under certain conditions such as read requests to the memory whose contents are currently in the cache. Write-Back allows the CPU to operate with fewer interruptions, increasing its efficiency.
Wr-Back / Write Back enabledWr-Thru / Write Through enabled
System BIOS Cacheable
When enabled, accesses to the system BIOS ROM addressed at F0000H-FFFFFH are cached, provided that the cache controller is enabled.
Enabled / BIOS access cachedDisabled / BIOS access not cached
Video BIOS Cacheable
As with caching the System BIOS above, enabling the Video BIOS cache will cause access to video BIOS addressed at C0000H to C7FFFH to be cached, if the cache controller is also enabled,
Enabled / Video BIOS access cachedDisabled / Video BIOS access not cached
Keyboard Controller Clock
Sets the speed of the keyboard controller.
7.16 Mhz. / DefaultPCICLKI/2 / 1/2 PCICLKI
PCICLKI/3 / 1/3 PCICLKI
PCICLKI/4 / 1/4 PCICLKI
ISA BUS Clock Option
The AT bus clock speed is the local speed at which the CPU communicates with memory. The speed is measured in terms of a fraction of the PCI bus speed represented by PCICLKI.
PCICLKI/2 / 1/2 PCICLKI (fastest) -- DEFAULTPCICLKI/3 / 1/3 PCICLKI
PCICLKI/4 / 1/4 PCICLKI
Keyboard Emulation
Enabling this allows the chipset to use its own internal, and much faster, Gate A20 function instead of the conventional, but slower, keyboard Gate A20. It also enables fast reset emulation
Enabled / Fast Gate A20 and Fast Reset enabledDisabled / Keyboard Gate A20 and Reset (Default)
Memory Hole Below 16Mb
When a value is selected, this allows the selected amout of RAM to be reserved for ISA adapter ROM. Selecting NONE disables the feature. The range of choices is between 64K upto 8M.
Slow Refresh (1/4 Freq)
This allows you to choose between the default, fast DRAM refresh and the slower, 1/4 speed refresh. This would be enabled if you were encountering data corruption because your DRAM was not fast enough to handle the fast timing.
Enabled / Slow refresh usedDisabled / Fast refresh used (Default)
I/O Recovery Time
The I/O recovery time is a programmed delay which allows the PCI bus to exchange data with the slower ISA bus without data errors. Settings are in fractions of the PCI BCLK.
2 BCLK / Two BCLKS. (Default)4 BCLK / Four BCLKS.
8 BCLK / Eight BCLKS.
12 BCLK / Twelve BCLKS.
HOST-to-PCI Post Write
This sets the delay used by the host CPU when performing a buffered write to the PCI bus.
0 WS / Zero wait states1 WS / One wait state (Default)
HOST-to-PCI Burst Write
When enabled the host CPU is allowed to use a write burst to the PCI bus.
Enabled / Bursting enabled on writes to the PCIDisabled / Burst writes not used (Default)
PCI Bus Park Option
This allows you to determine is any PCI device should be allowed to “park” on the PCI bus. Generally, the PCI controller arbitrates the bus by determining which device gains access to the bus for I/O. Enabling this feature allows a device to gain temporary, but sole access to the bus.
Enabled / PCI bus “parking” allowedDisabled / PCI bus “parking” not allowed (Default)
PCI Posted Memory Write
When enabled, the system will temporarily write data to a buffer so that the CPU will not be interruped or slowed down. When disabled, the memory write cycle for the PCI bus will be direct to the slower ISA bus.
Enabled / PCI posted writes are bufferedDisabled / PCI posted writes are not buffered
Burst Copy-Back Option
When enabled, if a cacheable CPU memory read results in a cache miss, then the chipset will initiate a burst cache line fill from main memory. The object is to maintain the status of the cache. When disabled, the cache will not be updated.
Enabled / Cache miss on CPU RAM read will cause second, burst read from RAM to cache.Disabled / Cache not affected by miss (Default)
HOST Clock / PCI Clock
This selection allows you to determine the speed of the PCI bus relative to the CPU’s internal clock, here assumed to be 1.
1 / PCI operates at same speed as the CPU (Default)1/2 / PCI operates at one-half the speed of the CPU.
Preempt PCI Master Option
When enabled, PCI bus operations can be preempted by certain system operations, such as DRAM refresh, etc. Otherwise, such operations can take place concurrently.
Enabled / PCI Master can be preemptedDisabled / PCI Master NOT preempted (Default)
IBC DEVSEL# Decoding
This allows you to set the type of decoding used by the ISA Bridge Controller (IBC) to determine which device to select. The longer the decoding cycle, the better chance the IBC has to correctly decode the commands. Choices are Fast, Medium and Slow (default).
Alt Bit in Tag SRAM
Tag bits are used to determine the status of the data held in the external cache, L2. This sets the level of error detection. If you have selected Write Back for the external, L2, cache, selecting 7+1 bits provides better error detection.
7+1 Bits / (Default)8+0 Bits / Alt bit always assumed active.
Award BIOS 4.5 Setup UtilityPower Management Setup § Page 1
Award Software
Power Management Setup
The Power Management Setup allows you to configure you system to most effectively save energy while operating in a manner consistent with your own style of computer use.
Power Management
This category allows you to select the type (or degree) of power saving and is directly related to the following modes:
1.Doze Mode
2.Standby Mode
3.Suspend Mode
4.HDD Power Down
There are four selections for Power Management, three of which have fixed mode settings.
Disable (default) / No power management. Disables all four modesMin. Power Saving / Minimum power management. Doze Mode = 1 hr. Standby Mode = 1 hr., Suspend Mode = 1 hr., and HDD Power Down = 15 min.
Max. Power Saving / Maximum power management -- ONLY AVAILABLE FOR SL CPU’S. Doze Mode = 1 min., Standby Mode = 1 min., Suspend Mode = 1 min., and HDD Power Down = 1 min.
User Defined / Allows you to set each mode individually. When not disabled, each of the ranges are from 1 min. to 1 hr. except for HDD Power Down which ranges from 1 min. to 15 min. and disable.
PM Control APM
When enabled, an Advanced Power Management device will be activated to enhance the Max. Power Saving mode and stop the CPU internal clock.
If the Max. Power Saving is not enabled, this will be preset to No.
Video Off Method
This determines the manner in which the monitor is blanked.
V/H SYNC+Blank / This selection will cause the system to turn off the vertical and horizontal synchronization ports and write blanks to the video buffer.Blank Screen / This option only writes blanks to the video buffer.
PM Timers
The following four modes are Green PC power saving functions which are only user configurable when User Defined Power Management (PM) has been selected. See above for available selections.
HDD Standby Timer
When enabled and after the set time of system inactivity, the hard disk drive will be powered down while all other devices remain active.
Doze Timer Select
When enabled and after the set time of system inactivity, the CPU clock will run at at slower speed while all other devices still operate at full speed.
Standby Timer Select
When enabled and after the set time of system inactivity, the fixed disk drive and the video would be shut off while all other devices still operate at full speed.
Inactive Timer Select
When enabled and after the set time of system inactivity, all devices except the CPU will be shut off.
Mode Control
The next three entries allow you to determine the speed of the CPU and the state of the display monitor during a power management mode. CPU speed is measured by the HCLK which is the host CPU’s default speed.
Doze Mode
CPU Speed: 1/4 HCLK (Default)Display: On (Default)
1/2 HCLK Off
Standby Mode
CPU Speed: 1/8 HCLK (Default)Display: Off (Default)
1/4 HCLK On
Inactive Mode
CPU Speed: STOP CLK (Default) CPU stops.
1/8 HCLK
Monitor Event In Full On Mode
The remaining power management entries allow you to determine which events are to be monitored while the system is in its normal, full on mode. When an item is enabled, the system will monitor the item for inactivity. When each enabled item has been inactive for the the time selected for the current PM mode, then the system will proceed to the next mode.
PCI MasterN Check
These four allow you to select each of the PCI slots for monitoring.
VESA Slave Access Check
This enables checking for activity on the VESA local bus.
LPT Access Check
Enables checking for activity by the parallel printer ports.
COM Access Check
Enables checking for activity at the COM, serial ports.
IDE Master & DMA Check
Enables checking for activity by the IDE hard drive controller and the DMA controller.
Floppy Access Check
Enables checking for activity at the floppy disk drives.
VGA Access Check
Enables checking for activity by the VGA controller.
Award BIOS 4.5 Setup UtilityPower Management Setup § Page 1
Award Software
PCI/Green Function Setup
This section describes configuring the PCI bus system and Green PC Wake-Up events. PCI, or Personal Computer Interconnect, is a system which allows I/O devices to operate at speeds nearing the speed the CPU itself uses when communicating with its own special components. This section covers some very technical items and it is strongly recommended that only experienced users should make any changes to the default settings.
PCI Slot Configuration
Slot x Using INT#
Some PCI devices use interrupts to signal that they need to use the PCI bus. Some devices, notably most graphics adapters, may not need an interrupt service at all. Each PCI slot is capable of activating up to four interrupts, INT# A, INT# B, INT# C and INT# D. By default, a PCI slot is allowed INT# A. Assigning INT# B has no meaning unless the device in the slot requires two interrupt services rather than just one. Likewise, using INT# C can only mean the device requires three interrupts and similarily for INT# D.
Selecting the default, AUTO, allows the PCI controller to automatically allocate the interrupts.
1st/2nd Available IRQ
A INT# is an interrupt request which is signaled to and handled by the PCI bus. However, since the operating system usually has the final responsibility for handling I/O, INT#s can be mapped to an IRQ if the device occupying a given slot requires an IRQ service. By default, IRQ’s 9 and 10 to PCI are mapped to PCI devices, but any available, unused IRQ can be used.
You can select which INT# is associated with each PCI slot and which conventional IRQ is associated with one of the two available INT#s. The IRQ settings must be the same as the jumper settings on the motherboard.
A setting of NA means the IRQ has been assigned to the ISA bus and is not available to any PCI slot.
PCI IRQ Activated by
This sets the method by which the PCI bus recognizes that an IRQ service is being requested by a device. Under all circumstances, you should retain the default configuration unless advised otherwise by your system’s manufacturer.
Choices are Level (default) and Edge.
PCI IDE IRQ Map to
This allows you to configure your system to the type of IDE disk controller in use. By default, Setup assumes that your controller is an ISA (Industry Standard Architecture) device rather than a PCI controller. The more apparent difference is the type of slot being used.
If you have equipped your system with a PCI controller, changing this allows you to specify which slot has the controller and which PCI interrupt (A, B,C or D) is associated with the connected hard drives.
Remember that this setting refers to the hard disk drive itself, rather than individual partitions. Since each IDE controller supports two separate hard drives, you can select the INT# for each. Again, you will note that the primary has a lower interrupt than the secondary as described in “Slot x Using INT#” above.
Selecting “PCI Auto” allows the system to automatically determine how your IDE disk system is configured.
WakeUp Event In Inactive Mode
The next set of selections allow you to configure the system to monitor activity on IRQs (Interrupt Requests). When an Enabled IRQ issues an interrupt, it will also cause the system to wake up.
IRQs supported are:
- IRQ3 (COM 2 )
- IRQ4 (COM 1)
- IRQ5 (LPT 2)
- IRQ6 (Floppy Disk)
- IRQ7 (LPT 1)
- IRQ8 (RTC Alarm)
- IRQ9 (IRQ2 Redir)
- IRQ10 (Reserved)
- IRQ11 (Reserved)
- IRQ12 (Reserved)
- IRQ13 (Coprocessor)
- IRQ14 (Hard Disk)
- IRQ15 (Reserved)
Award BIOS 4.5 Setup UtilityPower Management Setup § Page 1