Boston University Electrical and Computer Engineering

Boston University Electrical and Computer Engineering

SC571: VLSI Design Principles Lab #3: Buffer Chains

Due: March 19, 2002

GOAL: The goal of this lab is to achieve greater skill in layout using Cadence Virtuoso and to study the performance characteristics of circuits using transient simulation in Analog Environment. The student is recommended to use modularity concepts in this design activity.

DESIGN: You are asked to build, simulate, and study each of the three circuits below. Use the TSMC025 (min L = 0.3 um) device technology library for your layout and simulations. Assume VDD = 2.5 volts.

1.  A series of complementary CMOS buffers which are near optimal to drive a 15pF load. Assume that Cg=14fF for a 2 x 1 input gate (W=2 um, L=1 um). Let the pull-ups be such that rise and fall times are equal.

2.  A 3-stage complementary CMOS buffer chain whose stage ratio is approximately the cube root of the ratio of the load capacitance to the input gate capacitance.

3.  A 3-stage pseudo-NMOS buffer chain to drive the same load capacitance. Instead of designing this ratio circuit chain for equal rise and fall delays, design to achieve a VOL of 0.3 volts or less.

Compare the layout area, delay, and power for all three buffer chains.

SIMULATION:

1.  Drive the 15pF load for each circuit noting the rise and fall times and the delay times for each internal node and the output for each buffer chain.

2.  Use Extract in Cadence to build SPICE models based on your layouts and perform the simulations in Analog Environment using these models. Compare these results with simulations done from the schematics.

OUTPUT:

Demo your work to the GTF and make hard copies of circuit schematics, layouts, and simulation results for your report.

WRITEUP: Make a file called lab3p*.txt (*=1,2,3) listing rise, fall, and delay times of the signals at all nodes. Measure rise/fall times as 10-90% and delay times as 50% to 50% points on the circuit node waveforms. Explain the signals on the graphs, noting risetimes, falltimes, and delay times. Also, compute the power for each circuit assuming a square wave input waveform. List the total area of each of the three circuits.

NOTES:

1.  Use risetimes and falltimes of ~ 0.1ns. When you line up the cursor on input signals to make time measurements, line up on the midpoint values.

2.  Use pulse values of 2.5V and 0V.

3.  When laying out the inverter circuits, two options seem possible: 1. Brute force: layout of everything separately, or 2. Make the large buffer stages with a number of parallel transistor sections, with each section, in turn, containing a number of CMOS device poly gates in parallel. Try to use copy and paste techniques for this approach, as much as possible.

4.  Use the handout (from class) on how to optimally choose sizing for the complementary CMOS case as well as the pseudo-NMOS case.

5.  You will use transistor sizes based on the minimum design dimension of 0.3 um. Thus, the calculated optimal values may not be obtained precisely. You might want to alternate going a little over and a little under on alternate stages.

R. W. Knepper 2/27/02