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Background Statement for SEMI Draft Document 5823A
Revision to SEMI 3D2-1113,SPECIFICATION FOR GLASS CARRIER WAFERS FOR 3DS-IC APPLICATIONS
Notice: This background statement is not part of the balloted item. It is provided solely to assist the recipient in reaching an informed decision based on the rationale of the activity that preceded the creation of this Document.
Notice: Recipients of this Document are invited to submit, with their comments, notification of any relevant patented technology or copyrighted items of which they are aware and to provide supporting documentation. In this context, “patented technology” is defined as technology for which a patent has issued or has been applied for. In the latter case, only publicly available information on the contents of the patent application is to be provided.
Background
This Bonded Wafer Stack Task Force of the 3DS-IC Committee is developing documents that will provide the 3DS-IC community with the tools needed to define wafers used in each step of a 300 mm 3DS-IC process. This document is a major revision of SEMI 3D2, which was originally published in November 2013.Changes addressed issues that arose as the technology requirements developed. Table 2, which is the key section of this standard, was extensively revised, with several elements removed and others modified. To simplify use, the entire table was renumbered.
This document was developed in the Bonded Wafer TF of N.A. 3DS-IC Committee. The SNARF for the revision was approved by the 3DS-IC Committee in November 2014. Document 5823 failed ballot due to a number of editorial changes. This edition was approved for balloting in Cycle 6 or Cycle 7 of CY2015 by the 3DS-IC Committee in July 2015.
Review and Adjudication Information
Task Force Review / Committee AdjudicationGroup: / Bonded Wafer Stacks Task Force / NA 3DS-IC (Three-dimensional Stacked Integrated Circuits) Technical Committee
Date: / Tuesday, November 3, 2015 / Tuesday, November 3, 2015
Time & Timezone: / 10:30 AM to 12:00 Noon (U.S. Pacific Time) / 1:30 PM to 3:30 PM (U.S. Pacific Time)
Location: / SEMI Headquarters
3081 Zanker Road, San Jose, California 95134 / SEMI Headquarters
3081 Zanker Road, San Jose, California 95134
City, State/Country: / San Jose, California / San Jose, California
Leader(s): / Richard Allen (NIST) / Richard Allen (NIST)
SeshRamaswami (Applied Materials)
Chris Moore (BayTech-Resor)
Standards Staff: / Paul Trio (SEMI NA)
408.943.7041 / / Paul Trio (SEMI NA)
408.943.7041 /
This meeting’s details are subject to change, and additional review sessions may be scheduled if necessary. Contact Standards staff for confirmation.
Telephone and web information will be distributed to interested parties as the meeting date approaches. If you will not be able to attend these meetings in person but would like to participate by telephone/web, please contact Standards staff.
SEMI Draft Document 5823A
Revision to SEMI 3D2-1113,SPECIFICATION FOR GLASS CARRIER WAFERS FOR 3DS-IC APPLICATIONS
1 Purpose
1.1 This specification is intended to address the needs of the 3D Stacked IC (3DS-IC) industry by providing the tools needed to procure glass carrier wafers to be used in a 3DS-IC process.
2 Scope
2.1 This specification describes dimensional, thermal, and wafer preparation characteristics for glass starting material that will be used as carrier wafers in a temporary bonded state.
2.2 This Specification describes glass carrier wafers with nominal diameters of 200 and 300 mm, and a thickness of 700 µm, although the wafer diameter and thickness required may vary due to process and functional variation. Such variations shall be clarified in the purchasing order or in the contract.
2.3 Methods of measurements suitable for determining the characteristics in the specifications are indicated.
NOTICE: SEMI Standards and Safety Guidelines do not purport to address all safety issues associated with their use. It is the responsibility of the users of the Documents to establish appropriate safety and health practices, and determine the applicability of regulatory or other limitations prior to use.
3 Limitations
3.1 This document does not describe dimensions and procedures related to wafers and wafer stacks, 200 or 300 mm nominal diameter, with fiducials.
3.2 This specification does not describe glass for interposers or any other active or passive devices.
3.3 This specification does not describe glass wafers or panels for permanent bonding applications.
3.4 This document does not address issues associated with processing, bonding, or de-bonding.
4 Referenced Standards and Documents
4.1 SEMI Standards and Safety Guidelines
SEMI M1 — Specifications for Polished Single Crystal Silicon Wafers
SEMI 3D12 — Guide for Measuring Flatness and Shape of Low Stiffness Wafers
SEMI E119 — Mechanical Specification for reduced-pitch front-opening box for interfactory transport of 300 mm wafers
SEMI G90 — Specification for 300 mm coin-stack type shipping container used for test and packaging processes
SEMI M12 — Specification for Serial Alphanumeric Marking of the Front Surface of Wafers
SEMI M31 — Mechanical Specification for front-opening shipping box used to ship and transport 300 mm wafers
SEMI M35 — Guide for Developing Specifications for Silicon Wafer Surface Features Detected by Automated Inspection
SEMI M40 — Guide for Measurement of Surface Roughness of planar surfaces on polished wafers
SEMI M45 — Specification for 300 mm Wafer Shipping System
SEMI M59 — Terminology for Silicon Technology
SEMI MF533 — Test Method for Thickness and Thickness of Variation of Silicon Wafers
SEMI MF657 —Test Method for Measuring Warp and Total Thickness Variation on Silicon Wafers by Noncontact Scanning
SEMI MF671 — Test Method for Measuring Flat Length on Wafers of Silicon and other Electronic Materials
SEMI MF928 — Test Method for Edge Contour of Circular Semiconductor Wafers and Rigid Disk Substrates
SEMI MF1152 — Test Method for Dimensions of Notches on Silicon Wafers
SEMI MF1390 — Test Method for Measuring Warp on Silicon Wafers by Automated Non-contact Scanning
SEMI MF1451 — Test Method for Measuring Sori on Silicon Wafers by Automated Non-contact Scanning
SEMI MF1530 — Test Method for Measuring Flatness, Thickness, and Total Thickness Variation on Silicon Wafers by Automated Non-contact Scanning
SEMI MF1617 — Test Method for Measuring Surface Sodium, Aluminum, Potassium, and Iron on Silicon and Epi Substrates by Secondary Ion Mass Spectrometry
SEMI MF2074 — Guide for Measuring Diameter of Silicon and Other Semiconductor Wafers
SEMI T7 — Specification for Back Surface Marking of Double-sided Polished Wafers with a Two-Dimensional Matrix Code Symbol
4.2 ANSI Standards[1]
ANSI/ASQ Z1.4 — Sampling Procedures and Tables for Inspection by Attributes
ANSI 0P1.002-2009 — Optics and Electro-Optical Instruments - Optical Elements and Assemblies - Appearance Imperfections
4.3 ASTM Standards[2]
ASTM E122 — Standard Practice for Calculating Sample Size to Estimate, With Specific Precision, the Average for a Characteristic of a Lot or Process
ASTM E289 — Standard Test Method for Linear Thermal Expansion of Rigid Solids with Interferometry
ASTM C623 - 92(2010) Standard Test Method for Young's Modulus, Shear Modulus, and Poisson's Ratio for Glass and Glass-Ceramics by Resonance
4.4 ISO Standard[3]
ISO 14706 — Surface Chemical Analysis – Determination of Surface Elemental Contamination on Silicon Wafers by Total Reflection X-ray Fluorescence (TXRF) Spectroscopy
4.5 JEITA Standards[4]
JEITA EM-3401 — Terminology of Silicon Wafer Flatness
4.6 JIS Standards[5]
JIS H 0611 — Methods of Measurement of Thickness, Thickness Variation and Bow of Silicon Wafer
JIS H 0614 — Visual Inspection for Silicon Wafers with Specular Surfaces
4.7 MHIA Standard[6]
CEA 556-C — Outer Shipping Container Bar Code Label Standard
NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.
5 Terminology
5.1 Terms, acronyms, and symbols associated with silicon wafers and silicon technology are listed and defined in SEMI M59. Many of these terms and acronyms can be applied to wafers in a 3DS-IC process and to glass wafers as carriers.
5.2 General Definitions
NOTE 1:Many of these definitions are similar to, but slightly different from, those in SEMI M59. In many cases the definitions in SEMI M59 can be generalized to include 3DS-IC terms, but this is not being done at the present time.
5.2.1 Diameter — the diameter of the minimum circle that encloses the wafer.
5.2.2 Back surface — the surface of a wafer upon which the SEMI T7 mark appears.
5.2.3 Front surface— the surface of a wafer opposite to that with the SEMI T7 marking.
5.2.4 Glass carrier wafer — a glass wafer used for bonding to a device wafer temporarily during one or more process steps. A carrier wafer has neitheractive nor passive electrical parts.
5.2.5 Glass for interposers — glass substratewith openings intended for further processing into an interposer.
5.2.6 Wafer bond — a process by which two or more wafers are physically attached to each other using chemical and/or thermal and/or mechanical means.
5.2.6.1 Wafer bond, permanent — any wafer bond that is intended to remain through the lifetime of the bonded layers.
5.2.6.2 Wafer bond, temporary — any wafer bond that is intended to be debonded.
6 Ordering Information
6.1 Purchase orders for glass carrier wafers furnished to this specification shall include the items identified in Table 1 Part 2 by a symbol in the left-most column.
6.2 In addition, the purchase order must indicate the test method to be used in evaluating each of those items for which alternate test procedures exist.
6.3 Also, requirements for bulk, front and back surface defects, such as bubbles, scratches, edge chips and indents, and surface contamination requirements together with appropriate test methodology should be included in the purchase order
6.4 The following items must also be included in the purchase order:
6.4.1 Lot acceptance procedures,
6.4.2 Certification (if required),
6.4.3 Packing and shipping container labeling requirements.
7 Requirements for Standardized Glass Carrier Wafers for Temporary Bonding
7.1 Standard specifications for glass carrier wafers are listed in Table 1 Part 2. All of the parameters listed in the table and marked with a diamond symbol shall be included in the purchase order or contract.
7.2 Those specifications without a symbol should be included in the purchase order or contract but are not mandatory.
7.3 Some specifications leave optional values to be specified in the purchase order or contract. Those shall be included in the purchasing order or contract if they are considered mandatory requirements as indicated by a symbol.
7.4 If other types of glass wafers are required for an application or for research purposes, these may be ordered through the use of the glass carrier wafer specification order entry
Table 1Order Form for Glass Carrier Wafers for 3D Stacked IC Applications
Part 1 General Information
ITEM / INFORMATION / Date:1-1 / Customer Name
1-2 / Purchase Order Number
1-3 / Line Number
1-4 / Item Number
1-5 / General Specification Number
1-6 / Revision Level
1-7 / Part Number/Revision
Part 2 Standardized Specifications for 200 mm and 300 mm Glass Wafers for 3DS-IC Applications
Parameter / Requirement / Measurement method / 2-1 / Nominal Ground Edge Exclusion / [ ] None
[ ] Other, specify ______
/ 2-2 / Wafer ID Marking / [ ] SEMI T7
[ ] SEMI M12
/ 2-3 / Edge Surface Condition / [ ] Polished
[] Not Polished
/ 2-4 / Edge Chamfer / [ ] 200 µm ± 50 μm (for 300 mm glass wafers);
[ ] Other:______±_____m / SEMI MF928:
[ ] Method A,
[ ] Method B
[ ]Other:______
/ 2-5 / Diameter / [ ] 200.0 mm ±0.2 mm
[ ] 200.4 mm ±0.2 mm
[ ] 300.0 mm ±0.2 mm
[ ] 300.4 mm ± 0.2 mm
[ ] Other, specify _____ / [ ] SEMI MF2074
[ ] Other:______
/ 2-6 / Orientation Fiducial Mark#1 / [ ] Notch Depth: 1.00 mm +0.25 mm -0.00 mm
Notch Angle: 90.0 degrees +5 deg –1 deg
Flat (200mm only):
[ ] 195.50 ± 0.20mm
[ ] Other ______/ [ ] SEMI MF1152
[ ] SEMI MF671
/ 2-7 / Thickness, center point / [ ] 675 μm ± 5 μm
[ ] 700 m ± 5 m
[ ] Other, specify _____ / [ ] SEMI MF533
[ ] SEMI MF1530
[ ] JIS H 0611
[ ] Other:_____
/ 2-8 / Total Thickness Variation (GBIR) / [ ] ≤1 μm
[ ] ≤2 μm
[ ] Other, specify _____µm / [ ] SEMI 3D12
[ ] SEMI MF533
[ ] JIS H 0611
[ ] SEMI MF657 (partial scan)
[ ] SEMI MF1530 (full scan)
[ ] Other:_____
2-9 / Bow / [ ] ≤30 μm
[ ] ≤100 μm
[ ] Other:______/ [ ] SEMI 3D12
[ ] SEMI MF534
[ ] JIS H 0611
[ ] Other:______
/ 2-10 / Warp / [ ] ≤30 µm
[ ] ≤100 µm
[ ] Other:______/ [ ] SEMI 3D12
[ ] SEMI MF657
[ ] SEMI MF1390
[ ] Other:______
2-11 / Sori / [ ] ≤30 μm
[ ] ≤100 μm
[ ] Other:______/ [ ] SEMI 3D12
[ ] SEMI MF1451
[ ] JEITA EM-3401
[ ] Other:_____
2-12 / Young’s Modulus / [ ] Other, specify _____GPa / ASTM C623
/ 2-13 / Coefficient of Thermal Expansion (CTE) / [ ] 3310-7 1.5%
[ ] Other, specify _____ / ASTM E289
/ 2-13.1 / CTE Temperature range / [ ] 0 C – 300 C
[ ] Other, specify _____
2-14 / Surface roughness / [ ] <1.0 nm RMS
[ ] Other:____ / SEMI M40
/ 2-15 / Scratch/Dig / [ ] 20/10
[ ] 40/20
[ ] 60/40
[ ] Other ____/____ / ANSI 0P1.002-200
/ 2-16 / Bubbles / Inclusions / [ ] < 0.13 mm equivalent length (L+W)/2
[ ] Other, specify _____
/ 2-17 / Edge Chips / [ ] <0.5 mm
[ ] Other:______/ [ ] SEMI MF523
[ ] JIS H 0614
[ ] SSIS#2
[ ] Other:______
/ 2-18 / Edge Cracks / None / [ ] SEMI MF523
[ ] JIS H 0614
[ ] SSIS#2
[ ] Other:______
2-19 / Localized Light Scatterers (LLS) / Size: _____ m (LSE) Count: ______
per wafer; per cm2 (repeat for all sizes) / [ ] SEMI M35
[ ] SEMI MF523;
[ ] JIS H 0614;
[ ] SSIS;#2
[ ] Other:_____
2-20 / Surface metal contamination Alkali / [ ] [ ] × 10[ ] atoms/cm2 / [ ] ICP/MS;
[ ] AAS;
[ ] SEMI MF1617 (SIMS);
[ ] Other:_____
2-21 / Hazardous Substances Restrictions / Legislation ______
(repeat for all legislations)
/ 2-22 / Shipping Carrier / For 200 mm glass wafers:
[ ] 200 mm coin-stack shipping container
[ ] 200 mm vertical shipping box
For 300 mm glass wafers:
[ ] FOSB SEMI M31
[ ] FOSB SEMI E119 (reduced pitch FOSB)
[ ] 300 mm coin-stack shipping container – SEMI G90 / [ ] SEMI M45
#1Inscribed fiducials are not addressed by this document, but may be incorporated into this document at the appropriate time.
#2In today’s technology, it may be possible to inspect for some of these items using automated surface scanning inspection systems (SSIS). Such systems should be calibrated according to SEMI M53 using polystyrene latex spheres deposited in accordance with SEMI M58. Some indication of the defects separable by such instruments is provided in SEMI M35; however, a standard test procedure has yet to be developed. Application of automated inspection with the use of an SSIS must be agreed upon between supplier and customer.
7.5 General Characteristics
7.5.1 Edge Exclusion
7.5.1.1 The nominal edge exclusion, EE, specifies the diameter of the fixed quality area (FQA), which is given by the nominal diameter minus 2·EE (see Figure1). The fixed quality area is a center-referenced region that is independent in size from the tolerance of the wafer diameter. For the purposes of defining the FQA, the periphery of a wafer of nominal dimensions at a location with a notch is assumed to follow the circumference of a circle with diameter equal to the nominal wafer diameter.
7.5.1.2 The nominal edge exclusion for glass wafers is 0mm, unless otherwise stated in the purchase order or contract.
7.5.1.3 For equipment and/or procedures that are based on edge-referenced dimensions, the quality area is not fixed and some part of the fixed quality area may fall outside the evaluated area.
7.5.2 Wafer ID Marking— all glass wafers shall be marked with a two-dimensional matrix code symbol on the back surface outside the fixed quality area in the manner specified in SEMIT7. This marking shall be done as soon as practical after manufacture in order to provide both identification and traceability of each wafer.
7.5.2.1 Optionally, the user may specify an additional back-surface mark as shown in Figure1. This mark contains alphanumeric characters with the same message characters as the SEMIT7 mark, appropriate checksum characters as defined by SEMIM12 and character string as specified in SEMIM12:
NOTE 2:It is expected that this optional alphanumeric mark will not be used after users have developed successful experience with SEMIT7 mark usage.
7.5.2.2 Single density dot matrix, 5 dots horizontal and 9 dots vertical, shall be used.
7.5.2.3 Dot diameter shall be the same as that used for the two-dimensional matrix code symbol.
7.5.2.4 Character dimensions shall be as defined in Table 1 of SEMIM12 (nominal spacing = 1.42mm, nominal width = 0.812mm, nominal height = 1.624mm).
7.5.2.5 Mark location (center of bottommost dot rows) relative to the reference point of the SEMIT7 mark shall be 1.40 ± 0.05mm toward the wafer center, as shown in Figure1.
7.5.2.6 Mark field height, as defined by the distance between the centers of the topmost and bottommost dot rows of the A/N characters, shall be 1.62 ± 0.03mm (see Note 7).
7.5.2.7 Mark field length, as defined by the distance between the centers of the leftmost and rightmost dot columns of the A/N characters, shall be 16.43 ± 0.07mm.
7.5.2.8 The mark-field shall be centered on the radius that passes through the reference point of the SEMIT7 mark as shown in Figure1.
7.5.2.9 Character baseline shall be toward wafer OD and parallel with the row of the SEMIT7 mark that contains that mark’s reference point.
Figure 1:
Optional A/N Code Field Location on Back Surface of 200 mm and 300 mm Diameter Glass Wafers
NOTE:T7 field locations, from data matrix code symbol reference point to wafer center: r = 98.95 for 200 mm wafers and 148.95 for 300 mm wafers. A/N mark field dimensions are defined by the centers of the topmost and bottommost dot rows and the center of the leftmost and rightmost dot columns of the A/N characters. The field dimensions are more tightly controlled than those of a field constructed using SEMIM12. This results from the availability of laser marking capabilities not available when SEMIM12 was developed. In addition, the tolerance on the field dimensions is not cumulative.
7.6 Edge Characteristics
7.6.1 Edge Surface Conditions — method of finishing edges shall be described.
7.6.2 Edge Chamfer — Determine by methods agreed upon between the supplier and the customer. Method B of SEMI MF928 is a non-destructive way of evaluating the shape of the edge profile (see Figure 2 and Table 2-1.8 for the shape and dimensions of an appropriate template.
7.6.2.1 The edge chamfer shall be 200 ± 50 m for a 300 mm glass carrier wafer so that the edge of the wafer fits within the template shown in Figure 2 and Table 2-1.8, unless otherwise stated in the purchase order or contract.
Figure 2
Glass Wafer Edge Template Showing Edge Chamfer
Point / x-coordinate / y-coordinateA / 150 m / 0 m
B / 250 m / 0 m
C / 0 m / 250 m
D / 0 m / 150 m
Table 3:
Glass Carrier Wafer Taper Template Coordinates
7.6.3 Cosmetic attributes of the edge profile are not covered by either of these specifications. They shall be agreed upon between supplier and customer.
7.7 Dimensional Characteristics
7.7.1 Diameter — measured value
7.7.2 Fiducial Dimensions — all wafer produced to this specification shall have a fiducial. This is to meet alignment requirements of wafer processing tools.
7.7.2.1 Notch Dimension — the Notch Depthfor glass carrier wafers shall be 1.00 mm +0.25 mm/-0.00 mm and the Notch Angle 90.0 degrees +5 deg/-1 deg. unless otherwise specified (see Figure 3).
7.7.2.2 Flat Dimension — an alternate fiducial for 200 mm wafer only is a flat with diameter of 195.50 mm ± 0.20mm
7.7.3 Thickness, center point — this is the nominal wafer thickness, as measured.
7.7.4 Total thickness variation (GBIR) — the difference between the maximum and minimum values of the thickness of the wafer.
7.7.5 Bow – the deviation of the center point of the median surface of a free, unclamped wafer from a median-surface reference plane established by three points equally spaced on a circle with a diameter a specified amount less than the nominal diameter of the wafer.
NOTE 3:As for glass wafer diameters > 200 mm the deflection of the mount and the gravitational sag exceed the offered correction factors of conventional methods, the measurement technique described in SEMI 3D12 is recommended.
7.7.6 Warp — the difference between the maximum most positive and minimum negative distances of the median surface of a free, unclamped wafer from a reference plane within the fixed quality area. There are two forms of warp, one corrected for gravitational sag and the other not so corrected.