All Real World Signals Are Analog. the Processing Is, However, Done in the Digital Domain

CHAPTER 1

INTRODUCTION

All real world signals are analog. The processing is, however, done in the digital domain for most applications. Hence a good interface, an Analog to Digital Converter (ADC) is very much essential.

There are 2 types of data converters: Nyquist Rate converters and Oversampling data converters (ODC). The difference is that, while the former samples the input signal at the Nyquist frequency, the latter samples it at a very high frequency. The multiplicative factor is called the over sampling ratio. The Delta Sigma Modulator (DSM) falls under the second category. The advantage is that, a single bit ADC put in a feedback loop can simulate the performance of a 16 bit ADC. This reduces the number of components on the chip and thus the area.

The idea behind the DSM is that the signal and the noise are made to see different transfer functions. The non linear ADC is modeled as a linear ADC with uniformly distributed white noise added to it. The signal sees a unity gain while the noise is high pass filtered. When the output is passed through a low pass filter, the SNR increases; while the signal is unchanged, the noise in the signal band has decreased.

A second order loop filter consisting of two integrators have been used, in order to get a high SNR. Timing issues are crucial for the correct implementation of the DSM difference equations and therefore, the functioning of the circuit. Finally, Boser-Wooley feedback architecture has been used since stability will not be affected for the second order modulator, even if the coefficient at the input of the 2nd integrator is slightly altered. The entire system has been implemented in 180nm technology.

A complete MATLAB simulation was done. The MATLAB coefficients were translated to capacitor ratios by solving difference equations, in order to be implemented in the circuit. It was followed by the design of the individual blocks such as the first and the second integrator, the operational amplifier and latched comparator. The design was verified by plotting the impulse response of the loop filter. The complete ideal DSM simulation was done and the Power Spectral Density (PSD) was calculated and plotted.

Chapter 2

overview of adc’s

2.1 TYPES OF ADC

• FLASH ADC
• PIPELINED ADC
• SUCCESSIVE APPROXIMATION ADC
• INTEGRATING ADC
• RAMP-COMPARE ADC
• TIME INTERLEAVED ADC
• SIGMA-DELTA ADC

2.2 FLASH ADC

The flash ADC is the fastest type available in the world. A flash ADC uses comparators, and a string of resistors. A 4-bit ADC will have 16 comparators, an 8-bit ADC will have 256 comparators. Generally N-bit ADC will have 2N comparators. All of the comparator outputs connect to a block of logic that determines the output based on which comparators are low and which are high.

The conversion speed of the flash ADC is the sum of the comparator delays and the logic delay (the logic delay is usually negligible). Flash ADCs are very fast, but the disadvantage is that they consume enormous amounts of area and power.

2.3 SUCCESIVE APPROXIMATION CONVERTER

A successive approximation converter uses a comparator and counting logic to perform a conversion. The first step in the conversion is to check whether the input is greater than half the reference voltage. If it is, the most significant bit (MSB) of the output is set. This value is then subtracted from the input, and the result is checked for one quarter of the reference voltage. This process continues until all the output bits have been set or reset. A successive approximation ADC takes as many clock cycles as there are output bits to perform a conversion.

2.4 PIPELINED ADC

Pipeline ADC (also called sub ranging quantizer) uses two or more steps of sub ranging. First, a coarse conversion is done. In a second step, the difference to the input signal is determined with a digital to analog converter (DAC). This difference is then converted finer, and the results are combined in a last step. This can be considered a refinement of the successive approximation ADC wherein the feedback reference signal consists of the interim conversion of a whole range of bits (for example, four bits) rather than just the next-most-significant bit. By combining the merits of the successive approximation and flash ADCs this type is fast, has a high resolution, and only requires a small die size.

2.5 INTEGRATING ADC

Integrating ADC (also dual-slope or multi-slope ADC) applies the unknown input voltage to the input of an integrator and allows the voltage to ramp for a fixed time period (the run-up period). Then a known reference voltage of opposite polarity is applied to the integrator and is allowed to ramp until the integrator output returns to zero (the run-down period). The input voltage is computed as a function of the reference voltage, the constant run-up time period, and the measured run-down time period. The run-down time measurement is usually made in units of the converter's clock, so longer integration times allow for higher resolutions. Likewise, the speed of the converter can be improved by sacrificing resolution. Converters of this type (or variations on the concept) are used in most digital voltmeters for their linearity and flexibility.

2.6 RAMP-COMPARE ADC

Ramp-compare ADC produces a saw-tooth signal that ramps up, then quickly falls to zero. When the ramp starts, a timer starts counting. When the ramp voltage matches the input, a comparator fires, and the timer's value is recorded. Timed ramp converters require the least number of transistors. The ramp time is sensitive to temperature because the circuit generating the ramp is often just some simple oscillator. There are two solutions: use a clocked counter driving a DAC and then use the comparator to preserve the counter's value, or calibrate the timed ramp. A special advantage of the ramp-compare system is that comparing a second signal just requires another comparator, and another register to store the voltage value. A very simple (non-linear) ramp-converter can be implemented with a microcontroller and one resistor and capacitor. Vice versa a filled capacitor can be taken from an integrator, time-to-amplitude converter, phase detector, sample and hold circuit, or peak and hold circuit and discharged. This has the advantage that a slow comparator cannot be disturbed by fast input changes.

2.7 TIME INTERLEAVED ADC

Time-interleaved ADC uses M parallel ADCs where each ADC sample data every Mth cycle of the effective sample clock. This result is that the sample rate is increased M times compared to what each individual ADC can manage. In practice the individual differences between the M ADCs degrade the overall performance. However, technologies exist to correct for these time-interleaving mismatch errors.

2.8 SIGMA-DELTA ADC

The sigma-deltacircuits are used in applications requiring very high resolution at low speeds bits at 500Hz and audio converters (16 or more bits at 44 KHz), and they often work with very modest power budgets (2.3mW for an audio coder. For high resolution and/or low power at fairly low speeds (up to a few hundred KHz), Delta-Sigma Modulators (DSM) is the best ADC architecture choice.

The vast majority of delta sigma modulators have been built with Discrete-Time (DT) circuitry, very often switched-capacitor circuits. If circuit waveforms are to be allowed adequate settling time, the speed at which DT circuits are clocked must be restricted. These restrictions canberelaxed by employing Continuous-Time (CT) circuitry in place of DT circuitry. DSM hasresolution and power advantages over ADCs. DSM could retain these advantages even while operating at higher speed, this has been given increasing attention in the last few years as the need for high-resolution ADC at ever-higher speeds grows.

Delta sigma modulation is well suited for high-resolution analog-to-digital conversion since only modest demands are made on the accuracy of passive devices. Oversampling is used to shape the quantization noise from a coarse quantizer outside the signal band. The reasons why Continuous-Time Delta SigmaModulators (CT-DSMs) are attractive are the following. The bandwidth requirements of the active elements are greatly reduced when compared with a switched-capacitor implementation, thereby resulting in significant power savings. CT-DSMs also offer implicit anti-aliasing. Power reduction is a key motivator for using DSMs for digitizing low-frequency analog signals. Several implementations targeting the audio range have been reported recently. The first three of these designs use a single-bit quantizer.

2.9 APPLICATIONS OF DELTA-SIGMA MODULATORS

Pulse Width Modulation (PWM)

Music reproduction Technology (DOLBY)

Microcontrollers

Digital Oscilloscopes

Digital Video Cameras

Video Capture Cards

Voltage Monitor

A part of low-speed on-chip calibration engine

CHAPTER 3

BASICS OF SIGMA-DELTA CONCEPTS

3.1 DELTA SIGMA MODULATOR

Delta sigma modulator uses the concept of oversamplingand noise shaping. In delta sigma ADCs the sampling is done at a higher rate than the Nyquist rate to achieve higher resolution. Noise shaping is done by using a ADC in feedback to reduce the in band quantization noise and increase the out of band quantization noise thereby resulting in high SNR.

3.2 OPERATING PRINCIPLES

A delta-sigma ADC has three important components, depicted in Figure.3.1

1. A loop filter or loop transfer functionH(z).

2. A clocked quantizer.

3. A feedback digital-to-analog converter (DAC).

Figure.3.1 Components of a basic delta-sigma modulator

The basic idea of delta sigma modulation is that the analog input signal is modulated into a digital word sequence with a spectrum that approximates that of the analog input well in a narrow frequency range and has the quantization noise “shaped” away from this range. Linearising the circuit the quantizer is replaced by an adder as shown in Figure.3.2

Figure.3.2 Linearising the ADC in delta sigma modulator

The quantization noise is generated by an input e which is independent of thecircuit input u. The output y may now be written in terms of the two inputs u and e as

Where STF(z) and NTF(z) are the Signal Transfer Function and Noise Transfer Function.The poles of H(z) become the zeros of NTF(z) for any frequency where H(z) > 1,

Y (z) ≈ U(z):

In other words, the output resembles the input most closely at frequencies where the gain of H(z) is large.

3.3 OVERSAMPLING

A delta-sigma ADC is also known as an oversampling data converter. All other ADCs are sampled at the Nyquist rate. Hence they are called as Nyquist rate ADCs. In sigma-delta ADCs, however, the sampling is performed at a much higher rate than the Nyquist rate. The ratio of the sampling rate to the Nyquist rate is called the Over Sampling Ratio(OSR). Doubling the oversampling ratio reduces the quantization noise power resulting in 3dB SNR improvement.

In a given application, the signal bandwidth fin is usually fixed. Sampling faster than the Nyquist rate is always beneficial for improving the signal-to-noise ratio (SNR) in an ADC because the quantization noise inside the signal band is reduced by 3dB per octave of oversampling; in an delta sigma modulator, this improvement can be shown to be 6m + 3dB/oct (where m is the number of bits used for quantization) because the noise is shaped by the loop filter. Thus, a high-order modulator is desirable because of the huge increase in converter dynamic range (DR) obtained from each doubling of the OSR[8].

Fig.3.3 Oversampling

Using a high-order modulator has drawbacks. First, the stability of the overall system with H(z) above order two becomes conditional: input signals whose amplitudes are below but close to full scale can cause overload at the output of the integrators closer to the quantizer. As well, the placement of the poles and zeros of H(z) becomes a complicated problem. Finally, the design of the decimator increases in complexity and area for larger oversampling ratios. Typical values of OSR lie in the range 32–256[8].

3.4 ADVANTAGES OF OVERSAMPLING

Sample at fs 2fin.

Oversampling ratio OSR = fs/2fin.

Filter the noise using a filter of bandwidth fb = fs/(2*OSR).

Mean squared value of error =

Increased signal to quantization noise ratio.

Lower order anti-aliasing filter can be used

3.5 QUANTIZER RESOLUTION

It is possible to replace the single-bit quantizer with a multibit quantizer, e.g., a flash converter. This has two major benefits: it improves overall delta sigma modulators resolution and it tends to make higher-order modulators more stable. Furthermore, nonidealities in the quantizer (e.g., slightly misplaced levels or hysteresis) don’t degrade performance much because the quantizer is preceded by several high-gain integrators, hence the input-referred error is small. Its two major drawbacks are the increase in complexity of a multibit versus a one-bit quantizer, and that the feedback DAC nonidealities are directly input-referred so that a slight error in one DAC level corrupts converter performance greatly[7]. There exist methods to compensate for multibit DAC level errors. These aren’t needed in a single-bit design because one-bit quantizers are inherently linear. Even if these two levels are imprecise, the result is only offset and gain which is tolerable in DSM.

3.6 NOISE SHAPING

In Delta Sigma Modulator the noise is shaped so that most of the noise is concentrated only in the high frequency region. By noise shaping the in band quantization noise is minimized and the out of band quantization noise is maximized. If the noise is not shaped then when sampling is done, the noise gets added and the signal component becomes difficult to be differentiated from noise. So the noise is shaped such the in band noise is very small and when filtered using a low pass filter the signal component can be obtained with very low noise. This increases the SNR ratio.

Figure.3.4 First order noise shaping

The quantization noise spectrum of a typical Nyquist type converter and the theoretical SNR of such a converter is given in Figure 3.5. Figure.3.6 shows the effects of oversampling, fs/2 is much greater than 2fin and the quantization noise is spread over a wider spectrum. The total quantization noise is still the same but the quantization noise in the bandwidth of interest is greatly reduced. Figure.3.6 illustrates the noise shaping of the over sampled sigma delta modulator. Again the total quantization noise of the converter is the same as in Figure.3.6, but the in-band quantization noise is greatly reduced[9].

Figure.3.5 Nyquist converter quantization noise spectrum

Figure.3.6 Over sampled quantization noise spectrum

3.7 NOISE SHAPING USING FEEDBACK

Fig.3.7Second order modulator

NOISE TRANSFER FUNCTION:

SIGNAL TRANSFER FUNCTION:

If the frequency band of interest is around DC (0 , …. , fb), then by making A(z) > 1 , we have :

STF(z) ≈ 1 ; NTF(z) < < 1

3.8 MATLAB RESULTS:

Figure.3.8 Output of DSM

It can be seen that the number of transitions in the output is more when the instantaneous frequency of the sine wave increases ( i.e. the rising and falling portions of the sine wave ). Similarly, the number of transitions is less at the output in the maximum and minimum portions of the sine wave since the instantaneous frequency is less. Hence it can also be said that Delta Sigma ADC can also be used for Pulse Width Modulation (PWM).

Figure.3.9 FFT plot of the input signal

Figure.3.10 FFT plot of the low pass filtered signal

The quantized output is sent through a low pass filter for checking purposes. The FFT plot of both the input fig.3.9 and the low pass filtered signal fig 3.10 shows that both have the same frequency component in the frequency bin.

Figure.3.11 Signal and the noise spectrum

From Figure.3.11 it can be seen that the in band quantization noise is reduced and the out of band quantization noise is increased thereby shaping the noise as high pass filtered and increasing the SNR. SNR of 98.08dB (actual SNR of 16 bit ADC) is achieved by using a 1 bit ADC using DSM techniques.

3.9 MATLAB COEFFICIENTS

Figure.3.12 Block diagram of second order Delta Sigma modulator

The coefficients a1, a2, b1, c1, c2 has to be designed carefully to maintain the system to be a stable one. The values have been found using MATLAB simulation. All the coefficients has to be low for the system to be stable. c3 is found to be high since it is present at the end of the system and also it is the input to the comparator, it does not affect the system stability.

Using these coefficients as poles and zeros, the signal transfer function and the noise transfer function is calculated.