To Run Cadence, You Just Need to Have /Usr/Local/Apps/Bin in Your Path (This Is Valid Both

To run Cadence, you just need to have /usr/local/apps/bin in your path (this is valid both for the ECE and for the ENGR machines) i.e check your .chrc for this directory in your path.

To setup Cadence you must create a directory in which you can save your Cadence projects (example: "cadence"). Change your current directory to "cadence" (or whatever you called the directory for your Cadence projects). Once you have changed your current directory to your Cadence project directory, run the Cadence setup script by typing the following command at the terminal:

~cdsmgr/process/CDK1.4/tsmc025/setup

This sets your directory to work with the TSMC 0.25um process and copies the appropriate files to that directory.

You can now start DFII by typing "icfb" from that ‘cadence’directory.

The first window to open is the log window (also called CIW, which stands for Command Interpreter Window). It's good to keep it in a visible place, since everything you do will be echoed in there, along with reports on the success (or failure) of your commands.

Lets make an inverter.

1. Create a library for your new design:

From the library manager window:

File->New->Library
Type a new name, such as ECE471.

Under the heading "Technology File", choose "Compile a new techfile".
Then from the dropdown menu choose "TSMC 0.24u CMOS025/DEEP (5M, HV FET). Click OK

2. Create a new cell, where you will design the inverter:

In Library Manager:

Highlight your new library (TEST if that is what you chose).
File->New->Cellview

Choose library ECE471, cell name "inverter", view name "schematic", and Tool "Composer-Schematic". Click OK.

3. Design your circuit:

3.1 Placing components:

For this inverter, you will need an nmos transistor, a resistor, a capacitor, and power and ground nodes.
From Schematic window:

Add->Instance
Add Instance and Component Browser windows will open.
Make sure the Library in the Component Browser is set to NCSU_Analog_Parts.
Use the Component Browser window ( i is hot key for Component browser instantiate) and single click N_Transistors, then select nmos4 and place it. Do the same for PMOS under P-Transistors. Place the component. Esc hot key helps you to escape

Also, from the NCSU_Analog_Parts, get the symbols for vdd and gnd from Supply_Nets (they define the net names for the power and ground nodes).

Some Hot Keys are:

f - for recentreing screen, w- for placing wire, p for adding pins

Connect transistors according to schematic. Connect vdd and gnd to substrate of P and NMOS respectively.

Press i -> Basic->Supply->vdd

Press i ->Basic->Supply->vss

Click on NMOS press –q. Change the width to 4λ i.e 480nm.

Click on PMOS press –q. Change the width to 8λ i.e 960nm.

Add pins. Make sure that ‘in’ pin is type “input” and ‘out’ pin is type “output”.

Check and save your final design.

Making Symbols

Click on line in left menu.

Go to ADD->Shape->Circle.

Press ‘m’ for move and move the pins to your symbol design.

Simulating the Schematic

Go back to schematic->Tools->Analog Environment->Simulation->Netlist->Create final.

Now you will have netlist of schematic.

The first line indicates the path of your file. ~rathi/cadence/simulation/invert1_FO1/hspiceS/schematic/netlist/hspiceFinal

Create Lay out:

In view type layout. Change the tool to Virtuso.

Press i -> Browse->NCSU_Techlib_tsmc03d->nmos->layout

click on it-> Press c (for copy) -> and add one more instance

Click on NMOS and press ‘q’ change cell to PMOS.

Shift –f ->f

Click on NMOS and press q to change the size to match the schematic sizes. Do the same for PMOS.

Go to LSW Window and click on Metal1 drw window. Press ‘r’. Draw Metal 1 connecting both drains to each other.

In LSW ->Poly drw->Connect both the gates and extend poly to make input.

Press ‘i’->NCSU_Techlib_tsmc03d->ntap->layout and place it as shown in figure.

Do the same for p-tap.

In LSW-> Connect drain of NMOS to gnd and PMOS to vdd.

i-> NCSU_Techlib_tsmc03d ->M1-Poly ->layout and place it over poly to make connection of input to poly.

i-> M1-M2 . Add connector for out put.

You can also add m2-m3 connector if required for your design to go on multi levels.

Adding Pins:

Extend input and output by drawing Metal 1 and metal 3 respectively.

Create->Pin->edit terminal name to “in” Make I/O type to Input. Click on Display Pin Name Box. In Pin type click on M1.

Do same for out pin. But change the i/o type to Output and Pin type Type to Metal3.

Create pins for vdd and gnd. Its better if you make it type ‘inputoutput’. Pin type to metal1.

Check and save.

Verify DRC.

Your icfb window will show you errors if there is any.

Extracting Parasitics

Verify ->Extract->Set Switches-> Extract Parasitics Caps. Click OK. A new window like shown below will appear.

ICFB should show you no errors. There will a new cell called extracted in your Cadence Library Manager.

Open the extracted view. It will look like following figure.

In new window go on Tools->analog environment-> Simulations->Netlist->Create Final.

Now you will have new netlist containing extracted view.

The first line indicate the path of your file.