The Following Is from the Online 4Th Chapter of the 3Rd Ed. of the Textbook

ECE 5020 Homework 4

The following is from the online 4th chapter of the 3rd ed. of the textbook.

1. Analyze the problem of an inverter chain driving a large capacitive load, this led to the invention of logical effort. Let the first inverter be minimum size with Cin = 7fF. Let the final capacitance load CL = 28.672pF, as in I/O pad. Using a tau of 50pS, and include junction capacitance Cj.

a).Calculate the delay for N = 1 inverter, 2 inverters, 4 inverters, 6, and 12 inverters. Choose inverter sizes to minimize overall delay. Experiment with unequal inverter sizes effort in the N = 4 and 6 cases, and show that the delay always increases.

b) Show that the different N cases of 4, 6, and 12 follow the curve in Slide 25 (Sensitivity Analysis) of the textbook Logical Effort Lecture Slides.

c). Assume an SOI process so that junction capacitance can be neglected. Given a large path H, minimize the sum delay D = h*N by finding the optimum h (and thus N). Note that h^N = H

Problems 4.10, 4.12

4. Problem using Figure 4.16:

a). Change the final load capacitance from 20 to 72. Calculate h and gate size for each stage. Gate size is how many times larger than minimum.

b). From Part a), show that a design with fewer stages can be faster. Assume the complements of the off-path inputs are available.

c). Change the final load capacitance from 20 to 7200. Calculate h and the gate size for each stage. Discuss how you could speed up the design by adding more stages.