King Saud University Final exam
College of Engineering 1st Semester 1427/1428
Electrical Engineering Department
EE-315 Digital & Analog Electronic Circuits
Answer any 5 questions
Question 1:
A- For the circuit shown in Fig.1, assume ideal op-amp unless otherwise mentioned:
1. Name the feedback topology, and calculate the feedback factor.
2. Calculate Vo/Vi.
3. Assume R2 is replaced by a capacitor; draw the circuit and find Vo (t).
4. Assume the op-amp gain A is finite; find the expression for Vo/Vi.
B- For the circuit shown in Fig.2 calculate Vo/Vi and the input resistance Ri.
Question 2:
A- What is the purpose of using current source in ICs?
B- Name the best current source in terms of output resistance.
C- Name the best current source in terms of accuracy.
D- Name the best differential amplifier in terms of input resistance.
E- For the circuit in Fig.3 assume b is very high, VBE=0.7 V and VA=100V.
1. Find the values of all DC currents and voltages take VB1=VB2=0.
2. Find the differential gain Ad=Vo1/Vd (Vd = VB1 - VB2)
3. Find the common mode gain ACM=Vo1/VCM (VCM = VB1 = VB2).
4. Deduce the CMRR.
Assume the input resistance at Q5 is infinite for section 2. , 3.
Question 3:
A- What is the main difference between analog and digital electronic circuits?
B- State two advantages of negative feedback.
C- Draw the equivalent circuit of an ideal series-series feedback amplifier, Derive an expression for the input and output of the feedback amplifier: Rif, Rof.
D- a. For the circuit shown in Fig. 4 Calculate Vo and Io for Is=2mA.
b. Show that it can be a series-shunt feedback topology, calculate the feedback factor.
c. If r only is open circuited calculate the new feedback factor.
d. If R only is open circuited calculate the new feedback factor.
Question 4:
A) A CMOS inverter using VDD=5 V has (W/L)n=4mm/2mm, Vtn=|Vtp| =1V, mnCox = 35mA/V2, mpCox = 14mA/V2, the load capacitance is 1.2 pF and is operated at 100MHz.
1) Find the value of (W/L)p that would result in Qn and Qp being matched.
2) Draw the CMOS inverter and its voltage transfer characteristics. Label the different regions and the state of the transistors in each region.
3) Find VOL and VOH and NML.
4) Find the propagation delay tPHL, tPLH.
5) Find the dynamic and static power dissipation.
B) State the advantages and disadvantages of the Pseudo-NMOS over CMOS.
C) Design a CMOS logic circuit that realizes the function. Specify the size of all the transistors in terms of n and p of the basic inverter.
Question 5:
Consider the digital gate shown in Fig.5. Take VBE=0.75V, VCE = 0.35V for the transistors.
a) What family of digital circuit is this gate?
b) Q4 is different than all other transistors. How? Why?
c) Calculate the base voltage of all transistors, and the current I when all inputs are high.
d) Show that Q4 is off when all inputs are high.
e) Show that Q5 is always on.
f) How do (R2, R5 and Q6) improve the performance of the gate?
Question 6:
1- Name the circuit shown in Fig. 6, and determine the function of each output.
2- When all inputs are low: I1=5.6mA, I2=7.2mA, and I3=4mA, Calculate the voltage levels and the values of RC1, RC2, and R3.
3- Calculate the power dissipated by the gate.
4- Compare this gate with CMOS gate in terms of: a) power dissipation, b) size, c) speed and d) noise margins,
5- In what region do QX and QY operate?
Make the necessary assumptions.