1Bit Full Adder 1.VHDL Source : Half Adder.Vhd
수업명 / 전기전자컴퓨터 응용 실험
조 교 / 권 태환
이 름 / 심 호기
학 번 / 32011671
Report
3주차
1bit Full Adder
1.VHDL Source : half_adder.vhd
entity half_adder is
port(a, b : in bit;
c, s : out bit);
end entity half_adder;
architecture arch_adder of half_adder is
begin
s <= a xor b;
c <= a and b;
end architecture arch_adder;
2.VHDL Source : full_adder.vhd
entity full_adder is
port(a, b, cin : in bit;
cout : out bit;
sum : out bit);
end entity full_adder;
architecture arch_adder of full_adder is
component half_adder is
port(a, b : in bit;
c, s : out bit);
end component;
signal s1st, c1st, c2nd : bit;
begin
adder_1st :
half_adder port map(a, b, c1st, s1st);
adder_2nd :
half_adder port map(s1st, cin, c2nd, sum);
cout <= c1st or c2nd;
end architecture arch_adder;
3.Screen shot : Functional simulation waveforms
4.Screen shot : Timing simulation waveforms
4주차
8bit Ripple Carry Adder
1.VHDL Source : half_adder.vhd
entity half_adder is
port(a, b : in bit;
c, s : out bit);
end entity half_adder;
architecture arch_adder of half_adder is
begin
s <= a xor b;
c <= a and b;
end architecture arch_adder;
2.VHDL Source : full_adder.vhd
entity full_adder is
port(a, b, cin : in bit;
cout : out bit;
sum : out bit);
end entity full_adder;
architecture arch_adder of full_adder is
component half_adder is
port(a, b : in bit;
c, s : out bit);
end component;
signal s1st, c1st, c2nd : bit;
begin
adder_1st :
half_adder port map(a, b, c1st, s1st);
adder_2nd :
half_adder port map(s1st, cin, c2nd, sum);
cout <= c1st or c2nd;
end architecture arch_adder;
3.VHDL Source : RCA.vhd
entity RCA is
port ( x_in, y_in : in bit_vector(7 downto 0);
c_in : in bit;
sum_out : out bit_vector(7 downto 0);
c_out : out bit);
end entity RCA;
architecture arch_adder of RCA is
component full_adder is
port ( a, b, cin : in bit;
cout, sum : out bit);
end component;
signal c_inner : bit_vector(0 to 6);
begin
adder_0 :
full_adder port map (x_in(0), y_in(0), c_in, c_inner(0), sum_out(0));
c:
for i in 6 downto 1 generate
adder_1to6 :
full_adder port map(x_in(i), y_in(i), c_inner(i-1), c_inner(i), sum_out(i));
end generate;
adder_7 :
full_adder port map (x_in(7), y_in(7), c_inner(6), c_out, sum_out(7));
end architecture arch_adder;
3.Screen shot : Functional simulation waveforms
4.Screen shot : Timing simulation waveforms
5주차
Binary to Seven Segment Converter
1.VHDL Source : SevenSegment.vhd
entity SevenSegment is
port(S_in : in bit_vector(3 downto 0);
S_out : out bit_vector(6 downto 0);
S_carry : out bit);
end entity SevenSegment;
architecture behav of SevenSegment is
component bin2bcd
port(a : in bit_vector(3 downto 0);
b : out bit_vector(3 downto 0);
c : out bit);
end component;
signal s_inner : bit_vector(3 downto 0);
begin
converter1 :
bin2bcd port map (S_in(3 downto 0), s_inner(3 downto 0), S_carry);
S_out <= "1111110" when (s_inner = "0000") else
"0110000" when (s_inner = "0001") else
"1101101" when (s_inner = "0010") else
"1111001" when (s_inner = "0011") else
"0110011" when (s_inner = "0100") else
"1011011" when (s_inner = "0101") else
"1011111" when (s_inner = "0110") else
"1110000" when (s_inner = "0111") else
"1111111" when (s_inner = "1000") else
"1111011" when (s_inner = "1001") else
"1001001";
end architecture behav;
2.VHDL Source : bin2bcd.vhd
entity bin2bcd is
port(a : in bit_vector(3 downto 0);
b : out bit_vector(3 downto 0);
c : out bit);
end entity bin2bcd;
architecture behav of bin2bcd is
begin
process(a)
begin
case a is
when "1010" => b <="0000"; c<='1';
when "1011" => b <="0001"; c<='1';
when "1100" => b <="0010"; c<='1';
when "1101" => b <="0011"; c<='1';
when "1110" => b <="0100"; c<='1';
when "1111" => b <="0101"; c<='1';
whenothers => b <= a; c<='0';
end case;
end process;
end architecture behav;
3.Screen shot : Functional simulation waveforms
4.Screen shot : Timing simulation waveforms
6주차
Button SW 7seg conv.
1.VHDL Source : SW2bin.vhd
entity SW2bin is
port(SW : in bit_vector(15 downto 0);
CnvtoBin : out bit_vector(3 downto 0);
Com : out bit_vector(7 downto 0));
end entity SW2bin;
architecture behav of SW2bin is
begin
CnvtoBin <= "0001" when (SW = "1000000000000000") else
"0010" when (SW = "0100000000000000") else
"0011" when (SW = "0010000000000000") else
"0100" when (SW = "0001000000000000") else
"0101" when (SW = "0000100000000000") else
"0110" when (SW = "0000010000000000") else
"0111" when (SW = "0000001000000000") else
"1000" when (SW = "0000000100000000") else
"1001" when (SW = "0000000010000000") else
"0000" when (SW = "0000000001000000") else
"1010" when (SW = "0000000000100000") else
"1011" when (SW = "0000000000010000") else
"1100" when (SW = "0000000000001000") else
"1101" when (SW = "0000000000000100") else
"1110" when (SW = "0000000000000010") else
"1111" when (SW = "0000000000000001") else
"1111";-- 버튼 2개 눌림 등의 입력은 False 로 출력
Com <= "11111111" when (SW = "0000000000000000") else
"11111110";
endarchitecture behav;
2.VHDL Source : Button2Sevensegment.vhd
entity Button2Sevensegment is
port(S_in : in bit_vector(15 downto 0);
S_out : out bit_vector(6 downto 0);
Com_out : out bit_vector(7 downto 0));
end entity Button2Sevensegment;
architecture behav of Button2Sevensegment is
component SW2bin
port(SW : in bit_vector(15 downto 0);
CnvtoBin : out bit_vector(3 downto 0);
Com : out bit_vector(7 downto 0));
end component;
signal s_inner : bit_vector(3 downto 0);
begin
converter1 :
SW2bin port map (S_in(15 downto0), s_inner(3 downto 0), Com_out(7 downto 0));
S_out <= "1111110" when (s_inner = "0000") else
"0110000" when (s_inner = "0001") else
"1101101" when (s_inner = "0010") else
"1111001" when (s_inner = "0011") else
"0110011" when (s_inner = "0100") else
"1011011" when (s_inner = "0101") else
"1011111" when (s_inner = "0110") else
"1110000" when (s_inner = "0111") else
"1111111" when (s_inner = "1000") else
"1111011" when (s_inner = "1001") else
"1110111" when (s_inner = "1010") else
"0011111" when (s_inner = "1011") else
"1001110" when (s_inner = "1100") else
"0111101" when (s_inner = "1101") else
"1001111" when (s_inner = "1110") else
"1000111" when (s_inner = "1111") else
"1001001";-- 이 표시가 나오면 안됨
end architecture behav;
3.Screen shot : Functional simulation waveforms
4.Screen shot : Timing simulation waveforms
5.Programming 결과
지난번에 만든 BCD to 7Segment 를 개조해서 SW to 7Segment를 만들어 보았다. 버튼을
1개 누를 때, 해당 버튼에 해당하는 숫자, 문자가 출력되게 하였으며, 만약 버튼이 1개
이상으로 눌릴 경우에는 ‘F’ (false)를 출력하도록 했다.
7주차
4bit Up&Down Counter
1.VHDL Source : Switch.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Entity switch is
port(rst : in std_logic;
clk : in std_logic;
d_in : in std_logic;
d_out : out std_logic);
End entity switch;
Architecture arch_switch of switch is
Begin
process(rst, clk)
variable d_in_sig : std_logic;
Begin
if rst = '1' then
d_out <= '0';
d_in_sig := '0';
elsif rising_edge(clk) then
if d_in = '1' and d_in_sig = '0' then
d_out <='1';
else d_out <='0';
end if;
d_in_sig := d_in;
end if;
end process;
End architecture arch_switch;
2.VHDL Source : counter_4bit.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity counter_4bit is
port(rst : in std_logic;
clk : in std_logic;
inc : in std_logic;
dec : in std_logic;
cnt_out : out std_logic_vector(6 downto 0));
End entity counter_4bit;
Architecture arch_counter of counter_4bit is
begin
process(rst, clk)
variable cnt : std_logic_vector(6 downto 0);
begin
if rst = '1' then
cnt := "0000000";
cnt_out <= (others => '0');
elsif rising_edge(clk) then
if inc = '1' then
cnt := cnt + 1;
elsif dec = '1' then
cnt := cnt - 1;
end if;
cnt_out <= cnt;
end if;
end process;
End architecture arch_counter;
3.VHDL Source : UpnDown_Counter.vhd
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity UpnDown_Counter is
port(rst_t : in std_logic;
clk_t : in std_logic;
inc_btn : in std_logic;
dec_btn : in std_logic;
cnt_out_t : out std_logic_vector(6 downto 0));
End entity UpnDown_Counter;
Architecture arch_counter of UpnDown_Counter is
component switch
port(rst : in std_logic;
clk : in std_logic;
d_in : in std_logic;
d_out : out std_logic);
end component;
component counter_4bit
port(rst : in std_logic;
clk : in std_logic;
inc : in std_logic;
dec : in std_logic;
cnt_out : out std_logic_vector(6 downto 0));
end component;
signal in_inc : std_logic;
signal in_dec : std_logic;
signal in_bin : std_logic_vector(6 downto 0);
signal in_bcd : std_logic_vector(6 downto 0);
begin
input_inc :
switch port map (rst_t, clk_t, inc_btn, in_inc);
input_dec :
switch port map (rst_t, clk_t, dec_btn, in_dec);
inc_dec :
counter_4bit port map (rst_t, clk_t, in_inc, in_dec, in_bin);
cnt_out_t <= in_bin;
end architecture arch_counter;
4.Screen shot : Functional simulation waveforms
5.Screen shot : Timing simulation waveforms
8주차
Watch
1.VHDL Source : Watch.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity watch is
port(clk : in std_logic;
rst : in std_logic;
hour10 : out std_logic_vector(3 downto 0);
hour1 : out std_logic_vector(3 downto 0);
min10 : out std_logic_vector(3 downto 0);
min1 : out std_logic_vector(3 downto 0);
sec10 : out std_logic_vector(3 downto 0);
sec1 : out std_logic_vector(3 downto 0));
end entity watch;
architecture arch_watch of watch is
begin
process(clk, rst)
variable vhour10 : std_logic_vector(3 downto 0);
variable vhour1 : std_logic_vector(3 downto 0);
variable vmin10 : std_logic_vector(3 downto 0);
variable vmin1 : std_logic_vector(3 downto 0);
variable vsec10 : std_logic_vector(3 downto 0);
variable vsec1 : std_logic_vector(3 downto 0);
begin
if rising_edge(clk) then
if rst = '1' or vsec1 = "1001" then
vsec1 := "0000";
else
vsec1 := vsec1 + 1;
end if;
sec1 <= vsec1;
if rst = '1' or (vsec10 = "0101" and vsec1 = "0000") then
vsec10 := "0000";
elsif vsec1 = "0000" then
vsec10 := vsec10 + 1;
end if;
sec10 <= vsec10;
if rst = '1' or (vmin1 = "1001" and vsec10 = "0000" and vsec1 = "0000") then
vmin1 := "0000";
elsif vsec10 = "0000" and vsec1 = "0000" then
vmin1 := vmin1 + 1;
end if;
min1 <= vmin1;
if rst = '1' or (vmin10 = "0101" and vmin1 = "0000" and vsec10 = "0000" and vsec1 = "0000")then
vmin10 := "0000" ;
elsif vmin1 = "0000" and vsec10 = "0000" and vsec1 = "0000" then
vmin10 := vmin10 + 1;
end if;
min10 <= vmin10;
if rst = '1' or
(vhour10 /= "0010" and vhour1 = "1001" and vmin10 = "0000" and vmin1 = "0000" and vsec10 = "0000" and vsec1 = "0000") or
(vhour10 = "0010" and vhour1 = "0011" and vmin10 = "0000" and vmin1 = "0000" and vsec10 = "0000" and vsec1 = "0000") then
vhour1 := "0000";
elsif vmin10 = "0000" and vmin1 = "0000" and vsec10 = "0000" and vsec1 = "0000"
then
vhour1 := vhour1 + 1;
end if;
hour1 <= vhour1;
if rst = '1' or (vhour10 = "0010" and vhour1 = "0000" and vmin10 = "0000" and vmin1 = "0000" and vsec10 = "0000" and vsec1 = "0000")then
vhour10 := "0000";
elsif vhour1 = "0000" and vmin10 = "0000" and vmin1 = "0000" and vsec10 = "0000" and vsec1 ="0000" then
vhour10 := vhour10 + 1;
end if;
hour10 <= vhour10;
end if;
end process;
end architecture arch_watch;
2.Screen shot : Functional simulation waveforms
3.Screen shot : Timing simulation waveforms
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