Cover Letter
JIANBO WANG, Ph.D.
1331 N Golden Palomino Pl, Tucson, AZ 85715
Cell: (520) 270-3606
Email:
OBJECTIVES
Working in an environment that encourages creative thinking and recognizes my potential, engineering skills, as well as my education background
EDUCATION
University of Arizona;Tucson, AZ
Doctor of Philosophy in Physics (Experimental High Energy Physics) – July 2007
GPA 3.9 (Summa Cum Laude)
University of Arizona;Tucson, AZ
Masters of Science in Physics (High Energy Physics) – May 1999
GPA 3.9 (Summa Cum Laude)
Institute of Physics, Chinese Academy of Science, Beijing, China
Masters of Science in Physics ( Solid State Physics) – May 1993
GPA 3.9
Wuhan University, Wuhan, China
Bachelors of Science in Physics – July 1988
TECHNICAL SKILLS
· Strong skills in circuit design , debugging hardware and software problem
· Programming in I 2 C, SPI, UART, SMAAT interface
· Computer Language: C, C++, Java, Perl
· Operating Systems: Linux, Windows, UNIX
· Pattern Based Test circuit designing and programming on ETS364 Prober EG4090, TSK UF3000Ex-e
· PCB design & simulation tools: VeriBest, MentorGraphics, Cadence, Altium, TINA-TI spice
· Digital programmable device design: State machine design, Altera HDL, Altera FPGA, Verilog HDL
· Skillful in different tester systems, the short learning curve for any new system: Piranha SZ 3610, SZ M3650, VLCT (TI made), ETS500, ETS364
· Good self-learner and quick problem-solver
PROFESSIONAL EXPERIENCE
TEXAS INSTRUMENTS, Tucson, Arizona
Senior Test Engineer , October 2010 – Present
· Served as a test methodology, test hardware and software design , and yield loss analysis “to go” technical leader for various products such as temperature sensors, high precision and high performance challenging product testing, 10uV offset current shunt monitor, high speed 1ns delay comparators, high speed current shunt monitor with 1uS delay, at 10mV step
· Proposed and developed the methodology which utilizes the combination of the simulation, the quick breadboard realization, or the previous generations of silicon in test development to significantly shorten the test development time
· Successfully released 15 core products to market generating $60M+. More than 15 years of experience as a test engineer with strong technical and problem solving skills
· Validated complicated 32-site probe card and collected precise data in a week which takes three weeks normally
· Worked on the test strategies for the mixed-signal device on ATE and a prober, and designed the test system hardware and software
· Derived innovative and sophisticated equations to solve technical challenging problems and results were highly praised by test gurus.
· Optimized the test cost, the coverage, and test time for various TI analog and mixed signal ICs to drastically reduce the test cost.
· Developed automated and easy to reuse scripts applied to USCI interface: SPI, UART,I2C,
· Led the new process test development effort in scan chain, EEPROM, OTP digital test, package level trim.
· Developed the test solution for high current 2Amp power amplifier and designed both the test software and hardware for the test system.
· Mentored the new engineers and guided colleagues on the test hardware and software designs and implementation for ATE.
· Always willing to work overtime upon urgent requirements
Test Engineer , July 2007 – October 2010
· Developed a structure program used for all gamma buffers testing on VLCT, used as template by other test engineers
· Implemented a new data structure is easy to control data, test sequence, and to implement the correlation lockout on VLCT
· Created a new method of I 2 C programming is easy to use, read, reuse, and check, and cut 20-50% of test time
· Demonstrated an understanding and generating test limit guard banding on all products
University of Arizona, Physics Department, Tucson, Arizona
PhD Candidate, April 2001 – July 2007
TEXAS INSTRUMENTS, Tucson, Arizona
Test Engineer , April 2001 – July 2007
· Analysis of the experimental data from Fermi National Laboratory (Chicago, IL)
· Pursuit of PhD degree in high energy physics
· First engineer to use VLCT (very low cost tester) in Tucson, and technical support pf VLCT for Tucson site
· Developed test of low drift 9ppm/C voltage reference
RELATED EXPERIENCE
BROOKHEAVEN NATIONAL LAB, Upton, NY
Research Assistant , Sept 1995 – Nov 1995
· Studied the structure of the material by using x-ray
· Collected and analyzed experimental data
FERMI NATIONAL LAB, Chicago, IL
Research Assistant , May 1997 – April 2001
· Designed data acquisition modules with FIFO.
· Designed PCB, wrote a PC card driver in assembly language, and designed state machines.
· Assembled, test board, debugged the board, wrote system manual.
· Developed a deep latch system replacing the Altera PLD download cable (typically, the cable was for configuring systemboard)
JOURNAL PUBLICATIONS
A. Alavi-Harati et al., “Observation of Direct CP Violation in KS,L -> ππ Decays,” Physical Review Letters 83 , 22-32 (1999).
E. Abouzaid et al., “Final Results from the KTeV Experiment on the Decay KL -> π0γγ,” Physical Review D 77 , 112004 (2008).
PRESENTATIONS
J Wang, Sean Pinder "Alternatives apart from the QTMU for time and frequency measurements and tradeoffs including test time & accuracy" TUG2016, Colorado SRPINGS (2016)
PERSONAL ATTRIBUTES
Responsibility Perseverance Cooperation Integrity Motivation
Curiosity Hard-working Easy-going