1. Introduction

Digital systems operate on digital signals. The digital signals are a set of finite discrete levels as contrast to analog signals which are continuous in time domain. All signals in nature are analog, and thus can be interpreted by analog systems directly. For these signals to be interpreted by the digital system, require them to be converted from analog to digital form. Some of the examples of digital systems are:

Laptop / Desktop, calculator, Digital weighing machine, digital watches and timers, camera, video games, digital music recording, digital video game etc.

A digital system can be broadly classified as either a combinational or a sequential system. In combinational systems the output at any instant depends only on the inputs supplied at that instant of time i.e. Y(t) = F(X (t)). Examples of combinational systems are decoder, multiplexer, adder/subtractor, comparator etc. In sequential circuit the output depends on the present input and also on the previous inputs i.e. Y(t) = F(X(0,t), where x(0,t) is the input from time 0 to t. In x(0,t), t is the present instant. Examples of sequential systems are state machine, registers, counters, sequence detector etc.

A system can be implemented from its specifications and conversely the specification for an existing product can be found on analyzing the product. The relationship between the specification and implementation is shown in the figure below:

1.1.Analysis and Design of Digital Systems

Analysis of a system means determining its specification from its implementation. It helps in describing the functionality of the system i.e. what the system does and its other characteristics like physical shape and size, power requirement, input and output, working conditions etc. These characteristics become part of the specification of that system.

The design is the implementation of the specification. The implementation describes how the systems functions. The implementation describes how the system is constructed using the simpler components. Thus a digital system can be thought of as a network of modules, which can be simple gates to registers, to processing elements or the processor. These modules can then be implemented independently and interconnected to form a large system. This leads to a hierarchical implementation. There are basically two types of design implementation:

  1. Top-Down implementation:
  2. Bottom-up implementation:

The top-down approach is used to decompose the system into modules or subsystems those themselves can be further decomposed into smaller subsystems and this process repeated until no further decomposing is possible.

The bottom-up approach makes use of the interconnection of the existing components to form a subsystem e.g. flip-flops can be interconnected to form registers or counters, these subsystems then can be interconnected with other modules to form other subsystems and son on until the complete functionality is achieved.

Both the above approaches have a disadvantage, in top-down approach there is no systematical approach that assures that the decomposition at a particular level optimizes the final implementation, similarly, the bottom-up approach has the disadvantage that there is no standardsystematic approach that assures that the compositions of subsystem that result in a correct system specification. Also with increasing complexity of new designs this approach is nearly impossible to maintain

1.2 Abstraction Layers

In the beginning era of electronic, the design were based on putting the transistors together for implementing a given hardware. Soon the transistors were replaced by higher level of abstraction called gate level abstraction hiding the details of its predecessor i.e. transistor level abstraction.

With the increase in complexity, yet another higher level of abstraction evolved. This level was called “register transfer level”. This level included fewer details than the gate level. The RT level focused on how data transfer happen between registers, logic units and buses hence its name RT level.

Thefourth level which still much complex than the other level is called system level abstraction. This level still has lesser detail about register, functions, gate etc, and the designer is only concerned with the functionality of the system being designed, and describes the algorithm that is going to be implemented.

1.3Gajski-Kuhn (Y) chart

The abstraction layers can be understood by the Gajski-Kuhn (Y) chart.

Gajski-Kun diagram is used to understand the modelling of the digital system. According to this chart a digital system can be modeled in one of the three alternatives. These are illustrated in the figure.

Structural Modeling: According to this modelling style, a digital system can be constructed by interconnecting the available subsystems.

Functional /BehaviouralModelling: According to this scheme a digital system is described by its function in the form of number of statements.

Physical or Geometric Layout: This method makes use of the geometric properties of the system and its sub-components/sub-systems.

In the figure above each of these modelling is divided in five circles representing the hierarchical level of design. These five level are summarized in table below:

Hierarchical Level / Structural Level / Functional Level / Physical Level
Circuit Level / Transistors / Transfer Fn. (Diff Eqn) / Transistor Layout
Logical Level / Gates, FF / Boolean Logic / Std-Cells/ Module Plan
Register Transfer Level / ALU, Reg, MUX / Register Transfer Language / Macros, Floor Plans
Algorithm Level / Sub-Systems, FSM, Data-Paths / Algorithms / Blocks, Chips
System Level / CPU, Memory / System Specifications / Chip, Board, MCM, Physical Partitions.

The hardware design goes through top-down methodology or bottom-up methodologies. Most commonly used approach is top-down approach for each of the three domains and goes from top indicating concise system to more detailed abstraction level.

1.4HDL based Design Flow

The flow diagram shows various stages of the digital system design. It starts with an idea in our mind which is penned down on a sheet of paper or fed to some CAD tools for synthesis. It is then required to be functionally tested, if it pass the functional test then the prject is ready for physical implementation which is further required to be tested for timing constraints and finally taken for chip implementation. All these steps are illustrated in the figure and elaborated in the following paragraph.

Figure-: VHDL entity design step

1.4.1Design Entry:

There are two ways of design entry in the CAD system, these are Schematic Capture and second by writing source code in hardware description language such as VHDL or Verilog.

(i) Schematic Capture / (ii) Source Coding
Schematic Capture tool include a graphic interface having a collection of graphic symbols of components and the interconnects / Source coding in HDL describes the hardware circuit rather than a program to be executed on a computer.
Examples of such tools are: gEda, Eagle, …. / Examples of such languages are: very high speed IC Hardware Description Language (VHDL), Verilog Hardware Description Language (or simply Verilog).
Any sub-circuits previously created by the user can be made part of the library, and later the symbol of such circuit can be used by the designer in his circuit. Such method known as hierarchical design provide a good way of dealing with the complex design. / User can write code for commonly used sub-circuit and include such designs in the library. Any other coder/designer can later simply call these libraries in his source-code. This reduces the bourdon of rewriting the same code and thus provides a good way of dealing with the complex design.
Schematic Design entry does not provide portability into different CAD tools. / This method of design entry is supported by most organizations, thus provide design portability i.e. A circuit specified in VHDL can be implemented in different types of chips and with CAD tools provided by different companies, without having to change the VHDL specification.
This method is limited to simple to medium scale design entry, because a larger system is difficult to design using such method. / Portability coupled with the fact that VHDL is widely used, encourages sharing and re-use of VHDL described circuits.

1.4.2 Synthesis:

It is expected that whatever be the design entry method, the CAD system must be able to generate the logic circuit. So CAD system uses another tool called as the synthesis tools for this purpose.

Synthesis is the process of generating a logic circuit from an initial specification o the above step (design entry). These tools translates the VHDL code into a network of interconnected gates or putting the other way the synthesis provide the set of output logic expression that describes the logic function needed to realize the circuit. As emphasized earlier generating this step manually is difficult task for complex circuits. The CAD tools come to a great relief for optimizing the step of generating the output logic functions. The synthesized circuit using the CAD synthesizer is expected provide optimized circuit which can be built and tested using the simulators.

1.4.3 Simulation:

A circuit must perform the desired function. The functional verification of the logic circuit is done using the functional simulators. The input conditions are specified by the user, and the simulator evaluates the outputs produced by the expression. The user then checks the timing waveform produced by the simulator to see if functional requirements are met.


Figure 1.2: Simulation Technique

1.4.4 Physical Design:

If the functional requirements are met during functional simulation, the next step is to determine how to implement the circuit on the given chip. The physical design tool map a circuit specified in the form of logic expressions into a realization that make use of the resources available on the target chip.

e. Timing Simulation

In VHDL, there are two types of delay that can be used for modeling behavior, these are inertial delay that is commonly known as the propagation delay and transport delay that is the delay through the wires. The combined effect of these is that the real circuits exhibit the delay which significantly affects the operational speed. The timing simulators evaluate the expected delay of a designed logic circuit. The results of timing simulators can be used to determine if the generated circuit meets the timing requirement of the specification for the design.

f. Chip Configuration

On passing all the above steps, the circuit is actually implemented on the chip.
Programmable devices:

PLD (both the CPLD and FPGA) are simple and best suited for the development and educational purpose. Almost all the CAD system vendors like Altera, Cadence, Mentor Graphics, Synopsys, Synplicity, and Xilinx etc. provide their own tools and the development boards. These boards also have necessary keypads and displays for input and output, thus the circuit in the PLDs can be tested on board for proper functionality

Implementation of design on chips:

The final implementation could aim at standard IC, custom based or application specific ICs or PLDs (Programmable Logic Devices). A comparison among these is given below:

Chip Types / Advantage / Disadvantage
Standard Chips / The design involves choosing the right chip for the functionalities and integrate them to realize the complex function / With the improvement in technology, this method has become inefficient, consume more pace and the functionality and the design cannot be changed
Programmable logic chips / The design using these chips allows the chips to be configured to get different logic circuit and hence different functionality. These chips can be programmed number of times by the users. / Since the chips consist of large number of programmable switches to connect the logic circuit elements. These switches consume large and valuable chip area, thus limits the operational speed. At times PLDs may not meet the desired performance/ cost objectives
Custom-based chips / The custom-based design are the single chip design for a complex function which otherwise would need many ICs on a PCB. Such designs are suited for optimizing the specific task and should be preferred when huge quantities are to be produced, in which case of such design would be cheaper. / Such design generally takequiet a lot time, and if the quantities to be produced is less then cost of such design will be high. In such case a PLD may be used since it does not involve manufacturing cost.

CAD Tools

The various task involved in the design of the digital systems with the help of CAD tools are:

  1. Design Entry- This is the 1st step for entering of the circuit in the CAD system, we can enter the description, truth table or the schematic.
  2. Simulation- simulators are used to test the design generated from the design entry for its correct functioning, mentor graphics, ISIM.
  3. Synthesis- It is the process of translating the design entered to a physically realizable circuit using PLDs
  4. Post Synthesis Timing and simulation- This test is carried out to carry out functional testing as well as to ensure timing constraint
  5. Physical Design-This is the place and route phase in which the gates are placed and interconnected to complete the circuit. This is followed by the timing simulation so that the circuit meets the timing constraints.

VHDL uses a number of tools for the synthesis and simulation, some of the tools are listed below:

1. Xilinx 14.1 : Xilinx Company Inc.

2. Quartus II 7.2 : Altera Inc

3. Libero II : Actel Inc

4. Blue HDL : Blue Wave Inc

5.Synplicity: Synplicity Inc

6.Modelsim 6.2g : Mentor Graphics Inc

7.FPGA Adv 6.2 : Mentor Graphics Inc

8.Active HDL 7.3 SP1 : Aldec Inc

9.Riviera – PRO 2008.02 : Aldec Inc

10.Leonardo Spectrum (synthesis): Mentor Graphics Inc

11.FPGA Advantage: Mentor Graphics Inc

12.Encounter RTL : Cadence