ISE 10.1 Quick
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Preface
About ThisTutorial
TheISE10.1QuickStartTutorial is a hands-onlearningtoolfornewusersoftheISE softwareandforuserswhowishtorefresh theirknowledgeofthesoftware.Thetutorial demonstrates basicset-upanddesignmethodsavailableinthePCversionoftheISE software. Bytheendofthetutorial,youwillhave agreater understandingofhowto implementyourown designflow using theISE10.1 software.
AdditionalResources
Tofindadditionaldocumentation,seetheXilinxwebsiteat:
TosearchtheAnswerDatabaseofsilicon,software,andIPquestions andanswers, orto create atechnicalsupportWebCase,seetheXilinxwebsiteat:
ISEQuick Start Tutorial3
Preface:About This Tutorial
4ISEQuickStartTutorial
TableofContents
Preface:AboutThis Tutorial
AdditionalResources...... 3
ISE10.1QuickStartTutorial
GettingStarted...... 7
SoftwareRequirements...... 7
HardwareRequirements...... 7
StartingtheISESoftware ...... 8
AccessingHelp...... 8
CreateaNewProject...... 9
CreateanHDL Source...... 10
Creatinga VHDLSource ...... 10
UsingLanguageTemplates(VHDL)...... 11
FinalEditingoftheVHDLSource...... 12
Creatinga VerilogSource...... 13
UsingLanguageTemplates(Verilog)...... 14
FinalEditingoftheVerilogSource...... 15
CheckingtheSyntaxoftheNewCounterModule...... 15
DesignSimulation...... 16
VerifyingFunctionalityusingBehavioralSimulation...... 16
SimulatingDesignFunctionality...... 18
CreateTimingConstraints...... 19
EnteringTimingConstraints...... 20
ImplementDesignandVerifyConstraints...... 22
ImplementingtheDesign...... 22
AssigningPinLocationConstraints...... 23
ReimplementDesignandVerifyPinLocations ...... 24
DownloadDesigntotheSpartan™-3DemoBoard...... 25
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ISE 10.1QuickStartTutorial
TheISE 10.1QuickStart Tutorial provides XilinxPLDdesignerswithaquickoverviewof thebasicdesignprocess using ISE10.1.Afteryouhavecompletedthetutorial, youwill haveanunderstandingofhowtocreate, verify,andimplementa design.
Note:Thistutorial is designed for ISE10.1 on Windows.
Thistutorialcontainsthefollowingsections:
•“GettingStarted”
•“Createa NewProject”
•“CreateanHDLSource”
•“DesignSimulation”
•“CreateTiming Constraints”
•“ImplementDesignandVerify Constraints”
•“ReimplementDesignandVerifyPinLocations”
•“DownloadDesigntotheSpartan™-3DemoBoard”
Foranin-depthexplanationoftheISEdesigntools,seetheISEIn-DepthTutorialonthe
Xilinx®websiteat:
GettingStarted
SoftwareRequirements
Touse thistutorial, youmustinstallthefollowingsoftware:
•ISE10.1
FormoreinformationaboutinstallingXilinx® software,seetheISEReleaseNotesand
InstallationGuide at:
HardwareRequirements
Touse thistutorial, youmusthavethefollowinghardware:
•Spartan-3Startup Kit,containingtheSpartan-3Startup KitDemoBoard
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StartingtheISE Software
TostartISE,double-clickthedesktop icon,
orstartISEfrom the Startmenubyselecting:
Start→AllPrograms →Xilinx ISE10.1Design Suite 11 ->ISE→ProjectNavigator
Note:Your start-up path isset during the installation process and may differ fromthe oneabove.
AccessingHelp
Atany timeduringthetutorial,youcanaccessonlinehelpforadditionalinformation abouttheISEsoftwareandrelated tools.
ToopenHelp,doeitherofthefollowing:
•PressF1toviewHelpfor thespecifictoolorfunction thatyouhaveselectedor highlighted.
•LaunchtheISEHelp Contentsfrom theHelpmenu.It containsinformationabout creating andmaintainingyourcompletedesignflow inISE.
Figure1: ISEHelpTopics
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Createa New ProjectR
CreateaNewProject
Create a new ISEprojectwhichwilltargettheFPGAdeviceontheSpartan-3 Startup Kit demo board.
Tocreate a newproject:
1.SelectFileNew Project...TheNewProject Wizardappears.
2.TypetutorialintheProjectNamefield.
3.Enterorbrowsetoalocation(directorypath)forthenewproject. Atutorial subdirectoryis createdautomatically.
4.Verifythat HDLis selected from theTop-LevelSourceType list.
5.ClickNexttomovetothedevicepropertiespage.
6.Fill intheproperties inthetableasshownbelow:
♦ProductCategory:All
♦Family:Spartan3
♦Device:XC3S200
♦Package:FT256
♦SpeedGrade:-4
♦Top-LevelSourceType:HDL
♦SynthesisTool:XST(VHDL/Verilog)
♦Simulator: ISESimulator(VHDL/Verilog)
♦PreferredLanguage:Verilog(orVHDL)
♦Verifythat EnableEnhancedDesignSummaryisselected. Leavethedefaultvalues intheremainingfields.
Whenthetable iscomplete,yourproject properties willlook like thefollowing:
Figure2:ProjectDevice Properties
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7.ClickNexttoproceedtotheCreateNewSourcewindowintheNewProjectWizard.At theendofthenextsection,yournewproject willbecomplete.
CreateanHDLSource
In thissection,youwillcreatethe top-levelHDLfile foryourdesign.Determinethe languagethatyouwishtouseforthetutorial. Then,continueeithertothe“Creatinga VHDLSource”sectionbelow,or skiptothe“Creatinga Verilog Source”section.
CreatingaVHDLSource
Create a VHDLsourcefilefortheproject asfollows:
1.ClicktheNewSourcebutton intheNewProject Wizard.
2.SelectVHDLModuleasthesourcetype.
3.Typeinthe filenamecounter.
4.Verifythat theAddto projectcheckboxisselected.
5.ClickNext.
6.Declaretheportsforthecounterdesignbyfilling intheportinformationasshown below:
Figure3:DefineModule
7.ClickNext,thenFinishintheNewSourceWizard-Summarydialogboxtocomplete thenewsourcefiletemplate.
8.ClickNext,thenNext,thenFinish.
Thesourcefilecontainingtheentity/architecturepairdisplaysintheWorkspace,andthe counter displaysintheSourcetab,asshownbelow:
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CreateanHDLSourceR
Figure 4: New ProjectinISE
UsingLanguageTemplates(VHDL)
Thenextstepincreatingthenewsourceistoadd thebehavioraldescriptionforthe counter. Todo thisyouwilluseasimplecountercodeexamplefromtheISELanguage Templates andcustomizeitforthecounterdesign.
1.Placethecursorjustbelowthebeginstatement withinthecounterarchitecture.
2.OpentheLanguageTemplatesbyselectingEdit→LanguageTemplates…
Note:You can tile the Language Templates and the counterfile byselectingWindow→ Tile
Vertically tomake themboth visible.
3.Usingthe“+” symbol,browsetothefollowingcodeexample:
VHDL→SynthesisConstructs→CodingExamples→Counters→Binary →
Up/DownCounters →SimpleCounter
4.WithSimpleCounterselected,selectEdit→UseinFile,orselecttheUseTemplatein
Filetoolbarbutton.Thisstepcopiesthe templateintothecountersourcefile.
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5.ClosetheLanguageTemplates.
FinalEditingoftheVHDLSource
1.Addthefollowingsignaldeclarationtohandle thefeedbackofthecounteroutput belowthearchitecturedeclarationandabovethe firstbeginstatement:
signalcount_int:std_logic_vector(3downto0):="0000";
2.Customizethesourcefileforthecounterdesignbyreplacingtheportandsignalname placeholderswiththeactualonesasfollows:
♦replace alloccurrencesof<clock>withCLOCK
♦replace alloccurrencesof<count_direction>withDIRECTION
♦replace alloccurrencesof<count>withcount_int
3.Addthefollowingline belowtheendprocess;statement:
COUNT_OUT<=count_int;
4.Savethefilebyselecting File→Save.
Whenyouarefinished,thecountersourcefilewilllooklikethefollowing:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitiveinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entitycounteris
Port(CLOCK:inSTD_LOGIC; DIRECTION :inSTD_LOGIC;
COUNT_OUT:outSTD_LOGIC_VECTOR(3downto0));
endcounter;
architectureBehavioralofcounteris
signalcount_int:std_logic_vector(3downto0):="0000";
begin
process(CLOCK)
begin
ifCLOCK='1'andCLOCK'eventthen if DIRECTION='1'then
count_int<=count_int+1;
else
count_int<=count_int-1;
endif;
endif;
endprocess;
COUNT_OUT<=count_int;
endBehavioral;
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CreateanHDLSourceR
YouhavenowcreatedtheVHDLsourceforthetutorialproject.SkippasttheVerilog sections below,andproceedtothe“CheckingtheSyntaxoftheNewCounter Module”section.
CreatingaVerilogSource
Create thetop-levelVerilogsourcefilefortheprojectas follows:
1.ClickNewSourceinthe NewProject dialogbox.
2.SelectVerilogModuleasthe sourcetypeintheNewSourcedialogbox.
3.Typeinthe filenamecounter.
4.Verifythat theAddtoProjectcheckboxisselected.
5.ClickNext.
6.Declaretheportsforthecounterdesignbyfilling intheportinformationasshown below:
Figure5:DefineModule
7.ClickNext,thenFinishintheNewSourceInformationdialogboxtocompletethenew source filetemplate.
8.ClickNext,thenNext,thenFinish.
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ThesourcefilecontainingthecountermoduledisplaysintheWorkspace,andthecounter displaysintheSources tab, asshownbelow:
Figure 6: New ProjectinISE
UsingLanguageTemplates(Verilog)
Thenextstepincreatingthenewsourceistoadd thebehavioraldescriptionforcounter. UseasimplecountercodeexamplefromtheISELanguageTemplatesandcustomizeitfor thecounterdesign.
1.Placethecursoronthelinebelowtheoutput[3:0]COUNT_OUT;statement.
2.OpentheLanguageTemplatesbyselectingEdit→Language Templates…
Note:You can tile the Language Templates and the counterfile byselectingWindow→ Tile
Vertically tomake themboth visible.
3.Usingthe“+” symbol,browsetothefollowingcodeexample:
Verilog→SynthesisConstructs→CodingExamples→Counters→Binary →
Up/DownCounters →SimpleCounter
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4.WithSimpleCounterselected,selectEditRight Click→UseinFile,or select the Use Template in
Filetoolbarbutton.Thisstepcopiesthe templateintothecountersourcefile.
5.ClosetheLanguageTemplates.
FinalEditingoftheVerilogSource
1.Todeclareandinitializetheregister thatstoresthecountervalue,modifythe declarationstatement inthefirstlineofthe templateasfollows:
replace: reg[<upper>:0]<reg_name>;
with:reg[3:0]count_int=0;
2.Customizethetemplatefor thecounterdesignbyreplacing theportand signalname placeholderswiththeactualonesasfollows:
♦replace alloccurrencesof<clock>withCLOCK
♦replace alloccurrencesof<up_down>withDIRECTION
♦replace alloccurrencesof<reg_name>withcount_int
3.Addthefollowinglinejustabovetheendmodulestatementtoassigntheregistervalue totheoutputport:
assignCOUNT_OUT=count_int;
4.Savethefilebyselecting File→Save.
Whenyouarefinished,thecodeforthecounterwilllook likethefollowing:
modulecounter(CLOCK,DIRECTION,COUNT_OUT);
inputCLOCK;
inputDIRECTION;
output[3:0]COUNT_OUT;
);
reg[3:0]count_int=0;
always@(posedgeCLOCK)
if(DIRECTION)
count_int<=count_int+1;
else
count_int<=count_int-1;
assignCOUNT_OUT=count_int;
endmodule
You havenowcreatedthe Verilog sourceforthetutorial project.
CheckingtheSyntaxoftheNewCounterModule
Whenthesourcefilesarecomplete,checkthesyntaxofthedesigntofinderrorsandtypos.
1.Verifythat Implementationisselectedfrom thedrop-down listradio buttonsinthe Sources window.
2.Selectthe counterdesignsourceintheSources windowtodisplaytherelated processesintheProcesses window.
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3.Clickthe“+”nexttotheSynthesize-XSTprocesstoexpandtheprocess group.
4.Double-clickthe Check Syntax process.
Note:You must correct any errors found in your source files. You can check for errorsin the ConsoletaboftheTranscriptwindow.Ifyoucontinuewithoutvalidsyntax,youwillnotbeableto simulate or synthesize your design.
5.ClosetheHDLfile.
DesignSimulation
VerifyingFunctionalityusingBehavioralSimulation
Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter module. The test bench waveform is a graphical view of a test bench.
Create the test bench waveform as follows:
1.Select the counter HDL file in the Sources window.
2.Create a new test bench source by selecting Project → New Source.
3.In the New Source Wizard, select Test Bench WaveForm as the source type, and type
counter_tbw in the File Name field.
4.Click Next.
5.The Associated Source page shows that you are associating the test bench waveform with the source file counter. Click Next.
6.The Summary page shows that the source will be added to the project, and it displays the source directory, type, and name. Click Finish.
7.You need to set the clock frequency, setup time and output delay times in the Initialize
Timing dialog box before the test bench waveform editing window opens.
The requirements for this design are the following:
♦The counter must operate correctly with an input clock frequency = 25 MHz.
♦The DIRECTION input will be valid 10 ns before the rising edge of CLOCK.
♦The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK. The design requirements correspond with the values below.
Fill in the fields in the Initialize Timing dialog box with the following information:
♦Clock High Time: 20 ns.
♦Clock Low Time: 20 ns.
♦Input Setup Time: 10 ns.
♦Output Valid Delay: 10 ns.
♦Offset: 0 ns.
♦Global Signals: GSR (FPGA)
Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically.
♦Initial Length of Test Bench: 1500 ns.
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Design SimulationR
Leave the default values in the remaining fields.
Figure 7: Initialize Timing
8.Click Finish to complete the timing initialization.
9.The blue shaded areas that precede the rising edge of the CLOCK correspond to the Input Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define the input stimulus for the counter design as follows:
♦Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the counter will count up.
♦Click on the blue cell at approximately the 900 ns to assert DIRECTION low so that the counter will count down.
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Note: For more accurate alignment, you can use the Zoom In and Zoom Out toolbar buttons.
Figure 8: Test Bench Waveform
10. Save the waveform.
11. In the Sources window, select the Behavioral Simulation view to see that the test bench waveform file is automatically added to your project.
Figure 9:Behavior Simulation Selection
12. Close the test bench waveform.
Simulating Design Functionality
Verify that the counter design functions as you expect by performing behavior simulation as follows:
1.Verify that Behavioral Simulation and counter_tbw are selected in the Sources window.
2.In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process and double-click the Simulate Behavioral Model process.
The ISE Simulator opens and runs the simulation to the end of the test bench.
3.To view your simulation results, select the Simulation tab and zoom in on the transitions.
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Create Timing ConstraintsR
The simulation waveform results will look like the following:
Figure 10:Simulation Results
Note: You can ignore any rows that start with TX.
4.Verify that the counter is counting up and down as expected.
5.Close the simulation view. If you are prompted with the following message, “You have an active simulation open. Are you sure you want to close it?“, click Yes to continue.
You have now completed simulation of your design using the ISE Simulator.
CreateTimingConstraints
SpecifythetimingbetweentheFPGAanditssurroundinglogicaswellasthefrequency thedesignmustoperateatinternaltotheFPGA.Thetimingisspecifiedbyentering constraintsthatguidetheplacementandroutingofthedesign.Itisrecommendedthatyou enterglobalconstraints.Theclockperiodconstraintspecifiestheclockfrequencyatwhich your designmustoperateinside theFPGA.Theoffsetconstraintsspecifywhentoexpect validdataattheFPGAinputsandwhenvaliddatawillbeavailableattheFPGAoutputs.
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EnteringTimingConstraints
Toconstrainthe design dothefollowing:
1.SelectImplementationfrom thedrop-down listintheSourceswindow.
2.Selectthe counterHDLsourcefile.
3.Clickthe“+”signnexttothe UserConstraintsprocessesgroup, anddouble-clickthe
CreateTimingConstraintsprocess.
ISE runs theSynthesisandTranslatestepsandautomaticallycreatesa User
ConstraintsFile (UCF).Youwillbepromptedwiththefollowingmessage:
Figure11: Prompt toAddUCFFiletoProject
4.ClickYestoaddthe UCFfile toyourproject.
Thecounter.ucffileisaddedto yourproject andisvisibleintheSourceswindow. The XilinxConstraints Editoropensautomatically.
Note:You can also create a UCF file for your project byselectingProject→Create New
Source.
5.IntheTiming Constraintsdialog,double click on CLOCK under unconstrained clocks windows. Eenterthe period as 40following in the Period, Pad to Setup, and-
CLock to Pad fields:
♦Period: 40
♦Pade to Setup: 10
♦Clock to Pad: 10
6.Click create and OkPress Enter.
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CreateTimingConstraintsR
Aftertheinformationhasbeenentered,thedialog shouldlooklikewhatisshown below..
Figure12:CreatingTimingConstraints
7.SelectTimingConstraintsunderConstraintTypeintheTiming Constraintstaband thenewly createdtimingconstraintsaredisplayedasfollows:
Figure13:TimingConstraints
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8.Savethetimingconstraints.Ifyouarepromptedto rerun theTRANSLATEor XST
step,clickOKtocontinue.
9.ClosetheConstraintsEditor.
ImplementDesignandVerify Constraints
Implementthedesignandverifythatitmeetsthetimingconstraintsspecifiedinthe previous section.
ImplementingtheDesign
1.Selectthe countersource file intheSources window.
2.OpentheDesignSummarybydouble-clickingtheViewDesignSummaryprocessin theProcessestab.
3.Double-clickthe ImplementDesignprocessintheProcessestab.
4.Noticethat afterImplementationiscomplete,theImplementationprocesseshavea green checkmarknexttothemindicatingthattheycompletedsuccessfully without Errors or Warnings.
Figure14: Post ImplementationDesignSummary
5.LocatethePerformance Summarytable nearthebottomofthe DesignSummary.
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ImplementDesignandVerify ConstraintsR
6.ClicktheAllConstraintsMetlinkintheTimingConstraintsfieldtoviewtheTiming
Constraintsreport. Verify thatthedesignmeetsthespecifiedtimingrequirements.
Figure 15:AllConstraintsMetReport
7.ClosetheDesignSummary.
AssigningPinLocationConstraints
Specifythepinlocationsfortheportsofthedesignsothattheyareconnectedcorrectlyon theSpartan-3Startup Kitdemoboard.
Toconstrainthe design portstopackagepins,dothefollowing:
1.Verifythat counterisselectedintheSourceswindow.
2.Double-clickthe I/O Pin Planning(Plan Ahea) – Post Synthesis Floorplan Area/IO/Logic - Post Synthesis process foundinthe User Constraintsprocessgroup.TheXilinxPinout and Area Constraints Editor (PACE) Plan Ahead Tool opens.
3.Select the Package View tab.In the IO ports tab expand the Scalar ports.
- Select CLOCK and type T9 in the site field in the I/O ports properties tab. Click on Apply to confirm the changes.
- Similarly apply K13 as location for DIRECTION
- Expand the COUNT_OUT (4) in the IO ports tab and then select of the ports to apply constraints. COUNT_OUT[3] to Pin N14, COUNT_OUT[2] to pin L12, COUNT_OUT to pin P14 and COUNT_OUT[0] to pin K12.
4.In the Design Object List window, enter a pin location for each pin in the Loc column using the following information:
♦CLOCK input port connects to FPGA pin T9 (GCK0 signal on board)
♦COUNT_OUT<0> output port connects to FPGA pin K12 (LD0 signal on board)
♦COUNT_OUT<1> output port connects to FPGA pin P14 (LD1 signal on board)
♦COUNT_OUT<2> output port connects to FPGA pin L12 (LD2 signal on board)
♦COUNT_OUT<3> output port connects to FPGA pin N14 (LD3 signal on board)
♦DIRECTION input port connects to FPGA pin K13 (SW7 signal on board)
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Notice that the assigned pin locations are shown in blue:
Figure 16:PackagePin Locations
5.SelectFile→Save. You areprompted toselectthebus delimitertypebased onthe synthesistoolyouareusing.SelectXSTDefaultandclickOK.
6.ClosePlan AheadPACE.
NoticethattheImplementDesignprocesseshaveanorange questionmarknexttothem, indicatingtheyareout-of-datewithoneormoreofthedesignfiles.ThisisbecausetheUCF filehasbeenmodified.
ReimplementDesignandVerifyPinLocations
Reimplementthedesignand verifythattheportsofthecounterdesignare routedtothe package pinsspecifiedinthe previoussection.
First,reviewthePinoutReportfromthepreviousimplementationbydoingthefollowing:
1.OpentheDesignSummarybydouble-clickingtheViewDesignSummaryprocessin theProcesseswindow.
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2.SelectthePinoutReportandselecttheSignalNamecolumnheadertosortthesignal names.NoticethePinNumbersassignedtothedesignportsintheabsenceoflocation constraints.
Figure17: PackagePinLocationsPriortoPinLocationConstraints
3.Reimplementthedesignbydouble-clickingtheImplementDesignprocess.
4.SelectthePinoutReportagainandselecttheSignalNamecolumnheadertosortthe signal names.
5.Verifythat signalsarenowbeingrouted tothecorrectpackagepins.
Figure18: Package PinLocationsAfterPinLocationConstraints
6.ClosetheDesignSummary.
Download Design to the Spartan™-3 Demo Board
This is the last step in the design verification process. This section provides simple instructions for downloading the counter design to the Spartan-3 Starter Kit demo board.
1.Connect the 5V DC power cable to the power input on the demo board (J4).
2.Connect the download cable between the PC and demo board (J7).
3.Select Implementation from the drop-down list in the Sources window.
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4.Select counter in the Sources window.
5.In the Process window, double-click the Configure Target Device process.
6.The Xilinx WebTalk Dialog box may open during this process. Click Decline.
iMPACT opens and the Configure Devices dialog box is displayed.
Figure 19:iMPACT Welcome Dialog Box
7.In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG).
8.Verify that Automatically connect to a cable and identify Boundary-Scan chain is selected.
9.Click Finish.
10. If you get a message saying that there are two devices found, click OK to continue.
The devices connected to the JTAG chain on the board will be detected and displayed in the iMPACT window.
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11. The Assign New Configuration File dialog box appears. To assign a configuration file to the xc3s200 device in the JTAG chain, select the counter.bit file and click Open.
Figure 20: Assign New Configuration File
12. If you get a Warning message, click OK.
13. Select Bypass to skip any remaining devices.
14. Right-click on the xc3s200 device image, and select Program... The Programming
Properties dialog box opens.
15. Click OK to program the device.
When programming is complete, the Program Succeeded message is displayed.
On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running.
16. Close iMPACT without saving.
You have completed the ISE Quick Start Tutorial. For an in-depth explanation of the ISE design tools, see the ISE In-Depth Tutorial on the Xilinx® web site at:
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