VL7101 VLSI SIGNAL PROCESSING

QUESTION BANK

2 MARKS

  1. List out the applications of Digital signal processing in control system.
  2. What is FPL?
  3. What is medium granularity of a device. Give example
  4. What are the advantages of ASICs?
  5. What are the stages present in Design implementation in a CAD design circle
  6. Make note on dynamic power dissipation.
  7. What are the Classification by Granularity
  8. What are Fine-Granularity Devices
  9. What are the Classification of VLSI circuits
  10. What are Medium-Granularity Devices
  11. What are Large-Granularity Devices
  12. Compare ASIC and FPGA
  13. Define critical path of data flow graph?
  14. Define cutset and feed forward cutset?
  15. What is retiming and give the application of retiming?
  16. Explain the unfolding algorithm?
  17. What are drawbacks of pipelining and parallel processing?
  18. What is procedure to draw a constraint graph from a set of inequalities?
  19. What is application of fast parallel FIR filters?
  20. Explain about rank order filters?
  21. Draw the structure of 2*2 merge unit?
  22. What is mean by algorithmic strength reduction?
  23. Explain steps of the cook-toom algorithm?
  24. Represent given number x=1.01110011 into CSD format?
  25. What are properties of CSD number representation?
  26. Explain the Horner rule with own example?
  27. Evaluate the polynomial using sub expression elimination concept p(x)=x23+x17+x8+x5+x4+x
  28. Explain the iterative matching algorithm?
  29. What are properties of wave –pipelined implementation?
  30. What is mean by sub expression elimination?
  31. What is mean by wave pipelining?
  32. Define asynchronous wave pipelining?
  33. What is clock skew?

BIG QUESTIONS

  1. Briefly explain the Classification by granularity in FPGA technology
  2. Explain the different types of Benchmarks for FPLs
  3. Explain the requirements for DSP Technology
  4. Describe with the block diagram the CAD Design circle
  5. Categorize the routing schemes and Timing Estimates for a 32-bit adder
  6. Explain the architecture of a 4-bit array multiplier with a neat diagram.
  7. explain in detail the the types of FPGA Technology
  8. What are the DSP Technology requirements .
  9. Explain in detail the structure of a Logic cell .
  10. Explain in detail the Time estimation performed in a design.
  11. Explain the various routing schemes available .
  12. Make note on the parameters which are related with power dissipation and analyse the various methods by which it can be reduce
  13. For a Unsigned DA Convolution A third-order inner product is defined by the inner product equation y equals

Assume that the 3-bit coefficients have the values c[0] =2, c[1] = 3, and c[2] = 1.verify the LUT with an example, which implements f(c[n], xb[n])

  1. Explain the various methods by which the critical path can be reduced in an FIR structure.
  2. Consider a direct form implementation of FIR digital filter

y(n)=ax(n)+bx(n-2)+cx(n-3)

obtain an equivalent data broadcast FIR filter structure and fine grain pipelining structure. Compare the models.

  1. What are the advantages of using pipelining and parallel processing? Show how the power reduction takes place through pipelining and parallel processing with suitable equations.
  2. Briefly explain with the example the Distributed Arithmetic concepts
  3. What are the various methods available for retiming.
  4. Explain on the retiming usint cutset method
  5. Explain on the retiming usin cutset method and pipelining
  6. Explain the method by which the number of registers Can be reduced .
  7. With suitable examples explain the concept of clock minimization techniques.
  8. Explain the unfolding phenomenon with suitable examples.
  9. For the given DFG in figure below. Use clock period minimization retiming algorithm to minimize clock period (16)
  10. Using unfolding technique convert bit serial adder architecture for word length (w=4) into bit –parallel ripple carry adder architecture.
  11. Consider the 6 order FIR filter

Y(n)= ax(n)+bx(n-4)+cx(n-6) (16)

Draw a topology for this filter such that the clock period is limited by 1 multiply-add time. Do this without adding any new latches?

  1. Draw a block architecture for this structure in (a) for block size of 3. Rearrange this block structure such that the clock period of this block structure is one fourth of a multiply-add time.
  2. Derive a 2x3 convolution algorithm using modified cook toom algorithm with beta=0,-1, +1. Given the complexity of this algorithm.
  3. Construct a 2x2 convolution algorithm using cook-toom algorithm with beta= 0,1,-1. Given the complexity of this algorithm.
  4. Design a 3-parallel FIR filter?
  5. Design a 2-parallel fast FIR filter and draw the transposed structure for the same.
  6. Design a 8 point-DCT architecture using algorithm-architecture transformation
  7. Design a parallel rank-order filter with window size 5 and 2 level processing?
  8. Explain the following concepts
  9. Synchronous pipelining (8)
  10. Bundled data versus dual rail protocol (8)
  11. Explain the concept of wave pipelining? (16)
  12. Explain the concept of clock skew and clock distribution in bit level

Pipelined VLSI system? (16)

  1. Explain multiplicative number splitting algorithm with own example (16)
  2. Explain substructure matching process for given 4-tap FIR filter

Y(n)=1.01010000010*x(n)+0.10001010101* x(n-1) +0.10010000010*x(n-2)+ 1.00000101000*x(n-4)

  1. Explain the following concept with subject to sub expression elimination

a. Multiple constant multiplication (8)