@head: Max's Chips and Dips: Xilinx Unveils new Virtex-5 FPGA Architecture

@deck: Xilinx has just announced the fifth generation of its Virtex FPGAs, and these new Virtex-5 devices are simply incredible.

@text: I remember when the very first FPGAs appeared on the market circa 1984. They were rinky-dinky little things that were based on 3-input lookup tables (LUTs) and equated to relatively few logic gates. At that time, most digital design engineers thought of FPGAs as being slightly more sophisticated versions of simple PLDs; that is, these new components were considered to be suitable for gathering small chunks of "glue logic" together and maybe implementing simple state machines, but you wouldn’t want to use one for "real design work."How things have changed!

If you've not already heard, today (as this article is posted to the web), Xilinx has just announced the fifth generation of its Virtex FPGAs, and these new Virtex-5 devices are simply incredible. The first FPGAs to be created at the 65nm technology node, these little rascals use strained silicon for speed, low-K dielectrics to reduce parasitic effects, and 12-layer metal (11 copper, one aluminum) to implement a cunning new interconnect architecture.

Before we look at these rapscallions in a little more detail, it's worth summarizing some of the numbers that Xilinx are throwing around with gusto and abandon. As compared to their best-of-the-best Virtex-4 predecessors, the new Virtex-5 components offer 30% higher performance and 65% more logic cells. All of this is coupled with 45% area reduction, 35% lower dynamic power consumption and second-generation triple-oxide technology to maintain a low static power consumption.

So, What's Under the Hood?

Truth to tell, there's so much going on with this new family that it's difficult to know where to start. For example, the Virtex-V5 features 6-input LUTs; these reduce the number of logic levels and are particularly well suited to today's designs that boast wide data paths and wide logic/arithmetic functions. A Virtex-5 "slice" contains four of these 6-input LUTs, along with high-speed registers (to improve pipeline performance) and re-engineered high-performance fast-carry logic. Also, these little scamps have a new diagonal interconnect structure, which reduces the number of "hops" required to link logic blocks, minimizes delays, and improves predictability.

But wait, there's more. In addition to being boosted up to 32Kbits in size and 550 MHz in performance, the Virtex-5's new block RAMs contain hard IP to implement FIFOs, to realize simple dual-port RAM functions, and to perform 64-bit error checking and correction (ECC).

And don’t start me talking about the 550 MHz DSP slice with its 25 x 18 multiplier (the best offering from previous generations was 18 x 18). As if this wasn't enough, the multiplier is followed by a 3-input 48-bit "adder" (I say "adder" in quotes, because it can also perform logical operations such as AND, OR, XOR, etc.).

Clocks? You want to talk about clocks? Well, in addition to two digital clock managers (DCMs), the Virtex-5's new 550 MHz clock tile (and there can be lots of these tiles) also contains a phase-locked loop (PLL), which reduces reference clock jitter by more than 2x (the PLLs can be connected before the DCMs or after them depending on each design's unique requirements).

And when we come to the input/outputs (I/Os) … well, "Good Grief, Charlie Brown!" Now we can have up to 1,200 of the little rascals (around 25% more than the previous generation) providing 1.25 Gbps differential I/O and 800 Mbps single-ended I/O. All of this is combined with a new second-generation Sparse Chevron packaging technology, which is said to minimize cross talk and ease the task of PCB layout.

The Virtex-5 Family

All of the Virtex-5 devices are based on Xilinx's ASMBL(Advanced Silicon Modular Block) architecture. The idea here is that Xilinx have designed a suite of "columns", including a logic column, a memory column, a DSP column, and so forth. For each application domain – such as digital signal processing – Xilinx determine the optimum mixture (ratio) of logic, memory, DSP slices, and so forth. Next, Xilinx create a suite of components, all based on the same "mix" but with a range of capacities. This suite is collectively referred to as a "platform". Based on this, Xilinx have announced four domain-optimized platforms as follows:

  • The Virtex-5 LX Platform for high performance logic.
  • The Virtex-5 LXT Platform for high performance logic with serial connectivity.
  • The Virtex-5 SXT Platform for high performance DSP with serial connectivity.
  • The Virtex-5 FXT Platform for embedded processing with serial connectivity.

The Virtex-5 LX Platform is shipping now, with each of the remaining platforms slated for the second half of 2006 through the first half of 2007.

You Want More?

What? You want more? Well, of course there's …. but enough! I could go on for hours just hitting the high points. If you want to discover more, you can bet that the folks at Xilinx will be delighted to regale you with facts and figures until your brain overflows and you are aquiver with excitement. And so, I bid you adieu. Until next time, have a good one!

Virtex-5 FPGA Family Fact SheetPage 1May 2006