VHDL Tutorial Solutions

VHDL Tutorial Solutions

Question 1:

By looking at the input and output pins, it is clearly evident that A, B, C, D are input signals and Z is an output signal. This gives us an entity defined as in lines 1 to 4 below.

The equations for the lines in the diagram labelled E and F are required. Therefore, they are defined as signals in line 7 in the architecture. E is the output of the OR gate. One input of the OR gate is D and the other is the output of the AND of A, B and C. This gives us line 9 in the solution.

F is the output of the NAND gate. One input of F is A while the other is the NOR of B and C. Line 10 uses B nor C. This could have been described as not(B or C). This is the way the NAND gate is described in this line. Using the same type of description, then, line 10 could have been written as (B nor C) nand A.

Z is the output and depends on E and F. The equation is described in line 11. Note that using E and F in the description of the design makes it possible to monitor the signals at those points during simulation. This proves useful especially if you need to check if a signal is being delayed. For example, note that the circuit could have been minimized, especially the path through F. This path may have been deliberately designed to ensure that F does not change before E.

Solution (line numbers are provided for ease of reference):

1. entity Q1Tut is
2. port(A, B, C, D: in std_logic_vector;
3. Z: out std_logic_vector);
4. end Q1Tut;
5. architecture Answer of Q1Tut is
6. signal E, F: std_logic_vector;
7. begin
8. E <= (A and B and C) or D;
9. F <= not((B nor C) and A);
10. Z <= E xor not(F);
11. end Answer;

(2) (a) The one bit subtracter should have inputs A, B, and Carry In (Cin) producing outputs O = A-B-Cin and Carry Out (Cout). This description gives us the entity:

entity Subtracter

port (A, B, Cin: in std_logic;

O, Cout: out std_logic);

End;

The architecture is simply two equations, one for the input, one for the output.

Architecture Behavioral of Subtracter is

Begin

O <= (A and (B xnor Cin)) or (not(A) and (B xor Cin));

Cout <= (not(A) and (B or Cin)) or (A and B and Cin) ;

End Architecture Behavioral;

These equations can be clearly seen from the truth table:

2 (b) The four bit subtracter should have inputs A[3:0], B[3:0], and Carry In (Cin) producing output O[3:0] = A[3:0] – B[3:0] and Carry Out(Cout). This description gives us the entity:

entity Subtracter

port (A: in std_logic_vector(3 downto 0);

B: in std_logic_vector(3 downto 0);

O: in std_logic_vector(3 downto 0);

Cin: in std_logic;

Cout: out std_logic);

End;

The architecture needs to first identify the component called Subtracter that will be used, and then instantiate four components (i.e. create four instances of this component), one for each bit. The carry out of the lower bit will be connected to the Carry in of the next higher bit.

Architecture Behavioral of Subtracter is

Component Subtracter --declare that the component Subtracter will be used

port (A, B, Cin:std_logic

O, Cout: std_logic);

End component;

Signal Carry: std_logic_vector(3 downto 1);

Begin

Sub0:port map (A0, B0, Cin, O0, Carry1); --Subtracter for bit 0

Sub1: port map (A1, B1, Carry1, O1, Carry2);--Subtracter for bit 1

Sub2: port map (A2, B2, Carry2, O2, Carry3);--Subtracter for bit 2

Sub3: port map (A3, B3, Carry3, O3, Cout);--Subtracter for bit 3

End architecture Behavioral;

(3) From the question it is clear that the counter must be able to perform four operations:

(i)Clear the counter

(ii)Load the counter

(iii)Increment the value of the counter

(iv)Decrement the value of the counter

This implies that we must have:

(i)A clear input pin (CLR) that we will make active high and of highest priority.

(ii)A load input pin (LOADB) that will set the output pins to the value of four input pins.

(iii)Four input pins (D[3:0]) that will be used to load the output pins

(iv)Four output pins (O[3:0])

(v)A pin (UP) that indicates the output must be incremented.

(vi)A pin (DOWN) that indicates the output must be decremented.

This gives us the description:

Entity 74LS192 is

Port (D: in std_logic_vector (3 downto 0);

CLR, LOADB, UP, DOWN: in std_logic;

O: out std_logic_vector (3 downto 0));

End entity;

Architecture Behavioral of 74LS192 is

Begin

process (DOWN, UP, CLR, LOADB)

begin

If (CLR = ‘1’) then-- Clear counter

O <= “0000”;

Elsif (LOADB = ‘1’) then--Load counter

O <= D;

Elsif (Up = “1”) then--Increment counter

O <= O + 1;

Else-- Decrement counter

O <= O-1);

End if;

End process;

End architecture Behavioral;