Use of Bus Domain in Idesignspec(UVM Output)

Table of Content(ocp)
Table of Content
Index / Component / Default / Address / Page
1 / LH1256D_Chip / 0x0 - 0x3FFF
1.2 / AJMGW_Block / 0x0 - 0x3FF
1.2.1 / ControlReg / 0x0 / 0x0
0x0 - 0x3FF
1.3 / CDCMD_Block / 0x400 - 0x7FF
1.3.1 / CDCReg / 0x0 / 0x400
0x400 - 0x7FF
0x800 - 0x3FFF
Table of Content(wish)
Table of Content
Index / Component / Default / Address / Page
1 / LH1256D_Chip / 0x0 - 0x7FFF
1.2 / AJMGW_Block / 0x100 - 0x8FF
1.2.1 / ControlReg / 0x0 / 0x100
0x101 - 0x8FF
0x900 - 0x7FFF
Table of Content(amba2)
Table of Content
Index / Component / Default / Address / Page
1 / LH1256D_Chip / 0x0 - 0x7FFF
1.2 / AJMGW_Block / 0x100 - 0x8FF
1.2.1 / ControlReg / 0x0 / 0x100
0x101 - 0x8FF
0x900 - 0x7FFF
Table of Content(amba3)
Table of Content
Index / Component / Default / Address / Page
1 / LH1256D_Chip / 0x0 - 0x1FFF
1.3 / CDCMD_Block / 0x0 - 0x1FF
1.3.1 / CDCReg / 0x0 / 0x0
0x0 - 0x1FF
0x200 - 0x1FFF
Table of Content(prop_bus)
Table of Content
Index / Component / Default / Address / Page
1 / LH1256D_Chip / 0x4000 - 0x13FFF
1.3 / CDCMD_Block / 0x4000 - 0x4FFF
1.3.1 / CDCReg / 0x0 / 0x4000
0x4002 - 0x400F
1.3.2 / InternalSection / 0x4010 - 0x4011
1.3.2.1 / InternalReg / 0x0 / 0x4010
0x4012 - 0x4FFF
0x5000 - 0x13FFF
Table of Content(avalon)
Table of Content
Index / Component / Default / Address / Page
1 / LH1256D_Chip / 0x3000 - 0x6FFF
1.3 / CDCMD_Block / 0x3000 - 0x33FF
1.3.1 / CDCReg / 0x0 / 0x3000
0x3000 - 0x33FF
0x3400 - 0x6FFF
Table of Content(apb)
Table of Content
Index / Component / Default / Address / Page
1 / LH1256D_Chip / 0x2000 - 0x11FFF
1.3 / CDCMD_Block / 0x2000 - 0x2FFF
1.3.1 / CDCReg / 0x0 / 0x2000
0x2002 - 0x2FFF
0x3000 - 0x11FFF
Table of Content(axi)
Table of Content
Index / Component / Default / Address / Page
1 / LH1256D_Chip / 0x1000 - 0x8FFF
0x1000 - 0x10FF
1.1 / EDAHG_Block / 0x1100 - 0x18FF
1.1.1 / Section1 / 0x1100 - 0x1101
1.1.1.1 / DataReg1 / 0x0 / 0x1100
1.1.1.2 / DataReg2 / 0x0 / 0x1101
0x1102 - 0x18FF
0x1900 - 0x8FFF
Table of Content(amba1)
Table of Content
Index / Component / Default / Address / Page
1 / LH1256D_Chip / 0x0 - 0x1FFFF
1.1 / EDAHG_Block / 0x0 - 0x1FFF
1.1.1 / Section1 / 0x0 - 0x7
1.1.1.1 / DataReg1 / 0x0 / 0x0
1.1.1.2 / DataReg2 / 0x0 / 0x4
0x8 - 0x1FFF
0x2000 - 0x1FFFF

Use of Bus Domain in IDesignSpec(UVM Output)

Here, we describe how registers/section/block/chip can reside in multiple bus domains.

Bus Domain Name / Address Unit / Description / Bus
Busdomain
amba1 / 8 / This is AMBA-AHB bus. Since it is on top in this template,it becomes default bus for the register spec. / AMBA-AHB
amba2 / 32 / This is also AMBA-AHB, bus but with address unit 32 / AMBA-AHB
apb / 16 / This is AMBA-APB bus / AMBA-APB
ocp / 64 / This is OCP bus / OCP
axi / 32 / This is AMBA-AXI bus / AMBA-AXI
avalon / 64 / This is Avalon bus / AVALON
prop_bus / 16 / This is IDS Proprietary bus / PROPRIETARY
amba3 / 128 / This is AMBA3-AHB-lite bus / AMBA3AHBLITE
wish / 32 / This is Wishbone bus / WISHBONE

1 LH1256D_Chip

/ LH1256D_Chip / / amba1:0x0
axi:0x1000
apb:0x2000
avalon:0x3000
prop_bus:0x4000
amba3:0x0
amba2:0x0
wish:0x0
ocp:0x0
offset / external / size / 0x20000
oid=452e88ca-562b-41f0-a1fc-488c49962be1
{bus.domain=amba1,axi,apb,avalon,prop_bus,amba3,amba2,wish,ocp;offset.axi=0x1000;offset.apb=0x2000;offset.avalon=0x3000;offset.prop_bus=0x4000}
**This chip has "amba1" as the default bus.
**All buses specified here using "bus.domain" property would be used throughout to say which block/register resides in that domain

1.1 EDAHG_Block

/ EDAHG_Block / / amba1:0x0
axi:0x1100
offset / external / size / 0x2000
oid=f45275f7-d078-4762-b85d-fd094c915a23
{bus.domain=amba1,axi;offset.axi=0x100}
This block and it's registers reside in amba1 and axi domain

1.1.1 Section1

/ Section1 / / amba1:0x0
axi:0x1100
offset / external / repeat / size
oid=58fa5711-abcf-4648-a465-edc39452b3c9

1.1.1.1 DataReg1

/ DataReg1 / / amba1:0x0
axi:0x1100
offset / external / size / 32 / default / 0x0
oid=36193df1-7ee5-47f4-a181-c20daf905d01
bits / name / s/w / h/w / default / description
0:7 / CheckSumBits / ro / rw / 0
8:31 / DataBits / rw / ro / 0

1.1.1.2 DataReg2

/ DataReg2 / / amba1:0x4
axi:0x1101
offset / external / size / 32 / default / 0x0
oid=e8cab60a-b826-428d-bac6-afe5e52fd562
bits / name / s/w / h/w / default / description
31:0 / DataBits / rw / rw / 0
End RegGroup

1.2 AJMGW_Block

/ AJMGW_Block / / ocp:0x0
wish:0x100
amba2:0x100
offset / external / size / 0x2000
oid=40d7d729-f940-4fcb-b6d7-547304933a8d
{bus.domain=ocp,wish,amba2;offset.wish=0x100;offset.amba2=0x100}
This block and it's registers reside in ocp,wish and amba2 domain

1.2.1 ControlReg

/ ControlReg / / ocp:0x0
wish:0x100
amba2:0x100
offset / external / size / 32 / default / 0x0
oid=4d0ef5d7-a7c6-42ad-b594-f6f81ec2f0d6
bits / name / s/w / h/w / default / description
31:16 / FieldBits / ro / rw / 0

1.3 CDCMD_Block

/ CDCMD_Block / / ocp:0x400
avalon:0x3000
apb:0x2000
amba3:0x0
prop_bus:0x4000
offset / external / size / 0x2000
oid=c0132951-e515-44f6-8b6e-aaa44cf6522d
{bus.domain=ocp,avalon,apb,amba3,prop_bus}
This block and it's registers reside in ocp,apb,avalon,prop_bus and amba3 domain

1.3.1 CDCReg

/ CDCReg / / ocp:0x400
avalon:0x3000
apb:0x2000
amba3:0x0
prop_bus:0x4000
offset / external / size / 32 / default / 0x0
oid=6ae7ed18-80fb-4ba5-857b-5a37738d4df6
bits / name / s/w / h/w / default / description
31 / CDCBit / r/w1c / ro / 0
15:0 / FieldBits / rc / rw / 0

1.3.2 InternalSection

/ InternalSection / / prop_bus:0x4010
offset / external / repeat / size
oid=75af7c82-9d6e-42a3-8f0a-2afac202a00f
{bus.domain=prop_bus;offset.prop_bus=0x10}
This section and it's registers reside in proprietary bus domain

1.3.2.1 InternalReg

/ InternalReg / / prop_bus:0x4010
offset / external / size / 32 / default / 0x0
oid=0694295b-569e-44ad-a832-392e9b5ddd32
bits / name / s/w / h/w / default / description
31:0 / RegField / rw / rw / 0
End RegGroup

Note:Currently, IDS supports register sharing in UVM only