University of FloridaEEL 4712 Spring 1998Dr. Eric M. Schwartz

Department of Electrical & Computer EngineeringProfessor in ECE

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EEL 4712: DIGITAL DESIGN

Instructor:Dr. Eric M. Schwartz215 ffice Hrs: Tuesday, Periods 2-3

Class Meetings:MWF 8th period (3:00 p.m. – 3::50p.m.) in NEB 100 (but first class in Weil 270).

Lab Sections:4718 Mon 9-11 (MC)1516 Mon E1-E3 (BR)1518 Tues 2-4 (BR)

(NEB 212)1519 Tues E1-E3 (SM)4719 Wed 5-7 (MC)1517 Wed E1-E3 (SM)

Catalog Description: Advanced modular logic, design languages, finite state machines and binary logic.

Prerequisites: EEL 3701 (and CGS 3422 is a prerequisite for EEL 3701). Basic digital design and a working knowledge of one high level programming language (such as FORTRAN, BASIC, PASCAL or C) and an acquaintance with assembler language is assumed.

Textbook: Skahill, K., VHDL for Programmable Logic, Addison-Wesley, Reading, MA, 1996. (Be sure that the WARP CD-ROM is enclosed in the textbook: in the back cover.)

Additional Required Software:

  • Capilano Computing Systems, LTD., LogicWorks™ 3: Interactive Logic Circuit Design Software for Windows and MacIntosh, 1996, Addison-Wesley, New York.
  • LogicWorks™ web site:
  • LogicWorks™ (for Windows or MacIntosh) is available for purchase at the UF bookstore. This has been required in EEL 3701C for the last several years and is also used in EEL 4744C.

Technical Manuals:

  • Motorola High-Speed CMOS Data, by Motorola (DL129/D Rev 6)— given out in class
  • Motorola Fast and LS TTL Data, by Motorola — given out in class
  • PAL Device Data Book, Advanced Micro Devices — given out in class (hopefully)
  • PALASM User's Manual, 1990, and PALASM 4 Reference Guide, and PALASM 4 Getting Started, 1992, Advanced Micro Devices. Copies of selected pages will be made available at University Copy Center.

References:

  • Lam, H., & Arroyo, A. Fundamentals of Computer Engineering, Univ. Copy Center, Gainesville, FL, 1995.
  • Pellerin, David, and Taylor, Douglas, VHDL Made Easy!, Prentice-Hall, Inc., Upper Saddle River, NJ, 1997.
  • Yalamanchili, Sudhakar, VHDL Starter’s Guide, Prentice-Hall, Inc., Upper Saddle River, NJ, 1997.
  • Ashenden, Peter J., The Designer’s Guide to VHDL, Morgan Kaufmann Publishers, Inc., San Francisco, CA, 1996.
  • Dewey, Allen, Analysis and Design of Digital Systems with VHDL, PWS Publishing Company, Boston, MA, 1997.
  • Adamson, Thomas A. Digital Systems, Logic and Applications, Delmar Publishers Inc., Albany, NY, 1989.
  • Bignell, James W., & Donovan, Robert L., Digital Electronics, Delmar Publishers Inc., Albany, NY, 1994.
  • Bolton, Martin, Digital Systems Design with Programmable Logic, Addison-Wesley Publishing Company, Wokingham, England, 1991.
  • Comer, David J., Digital Logic and State Machine Design, Saunders College Publishing, Fort Worth, 1995.
  • Roth, C. H., Fundamentals of Logic Design, West Pub. Co., St. Paul, 1985.
  • Wiatrowski and House, Logic Circuits and Microcomputer Systems, McGraw-Hill, New York, 1980.

Office Hours: You may see any TA for consultation, not just the one teaching your lab section.

TA name / Michael Cerrato / Suresh Marimuthu / Barry Rodgers
office hours / M,W,F: 3rd; Th: 10th-11th / Th: 5th, F: 10th-11th / M,W,F: 3rd; Th: 2nd-3rd; F: 4th-5th
e-mail / / /

Closed Lab (NEB 212) Hours: M-F: 1st, M,W,F: 2nd, M,W,F: 8th; F: 9th, E1-E3.

I will hold office hours (as shown above)or by appointment. If you come by at any other time, I reserve the right to say “I’m busy,” although this is rarely the case. The use of e-mail is greatly encouraged to communicate with instructor/TAs.

Exam Schedule:

Exam / Date / Time
Exam 1 / Friday, 6 February 1998 / In Class
Exam 2 / Monday, 23 March 1998 / In Class
Exam 3 / Wednesday, 15 April 1998 / In Class
Final Exam / Tuesday, 28 April 1998 / 5:30p.m.-7:30p.m.

MULTIMEDIA CLASS/AUDIENCE HANDOUTS

Audience notes will sometimes be available from the University Copy Center (UCC) Monday mornings for that particular week’s classes. Sometimes these notes will be available after a week of classes. They consist of copies of the class overheads with space for note taking. These notes are not required but are highly recommended. At other times, these notes will be made available the Monday after a week of classes.

Course Requirements:

  1. Perform all laboratory experiments. Labs must be done at scheduled times. Late lab reports are not accepted. A lab grade of 65% or higher is required to be eligible to pass the class!
  2. Do all homework assignments. Late homework are not accepted.
  3. Take 3 during-term exams and a comprehensive final exam. No makeup exams will be given except for medically documented incapacity or family emergency.

Homework And Exam Solutions: Solutions to some of the homework will be made available on our class web-site. You may also purchase a copy of homework solutions at UCC. Exam solutions will be posted outside the lab area on the day the graded exams are returned to the class.

Cheating: Cheating will not be tolerated. You may talk to other students about homework assignments and labs, but the final work must be your own. If you are caught cheating on any assignment (homework, labs, quizzes or exams), your score for that assignment will be a 0, and a meeting with the instructor will determine the options open to you, none of which are desirable or pleasant (i.e., cheating may result in your failing the course, being brought up on honor court charges, and/or expulsion).. If you know some one who is cheating, it is your responsibility to report it.

Homework Grading: Homework are due at the start of the class period. When homework are returned, students should compare their solutions to the posted solutions since grading errors do occur. Late homework will not be accepted.

Laboratory Grading: Grading emphasis will be placed upon your producing well documented, well structured designs that realize the functional requirements specified by the lab handout and the lab instructor. The remaining portion of your grade will result from observations by your lab instructor on such matters as your understanding of the lab, your lab techniques, your prelab preparation and your cooperation and compliance with the rules. Lab reports are due at the start of your subsequent regularly scheduled lab. Late lab reports will not be accepted. You may not enter the lab without the necessary prelab preparations. See Laboratory Guidelines.

Exam Re-grade Policy: If you believe an error has been made on an exam score you must make a written request to me explaining where the misgrading or error occurred. This request must be submitted immediately at the end of the class in which the exam is returned. If you do resubmit an exam, however, I reserve the right to scrutinize and grade the entire exam more closely. This definitely places your current score at risk. Consequently, it is not advisable to resubmit an exam for correction unless a blatant error, such as a miscalculation of total points, has been made.

Course Grade Determination:

  • Exams @ 13.3% x 340%
  • Laboratory*25%(grade of 65% required to pass)
  • Homework10%(there will be between 8 and 10 homework assignments)
  • Comprehensive Final*25%(If Final  90, then Grade  Grade + ½ Letter)
  • Total100%

Part of your grade on tests, quizzes, labs, etc. is based not only on solving the problem you are presented with, but the manner in which you solve it. For example, there is a difference between two programs that meet the given specifications, but one is an elegant, extensible 20-line solution, while the other is a obfuscated 100-line program that also meets the specifications but would be difficult to extend later. Just as your future employer would value the latter program less than the first, so will I in grading your exams."

Handouts: If you miss a class in which a handout is made, you may pick it up on a table outside the Lab (we place additional copies there, but we cannot be responsible if students abuse the system). Please do not ask me or a Teaching Assistant for handouts! Some handouts will also be available from class web site.

EEL 4712C SCHEDULE

University of FloridaEEL 4712 Spring 1998Dr. Eric M. Schwartz

Department of Electrical & Computer EngineeringProfessor in ECE

Page 1/4SYLLABUS22-Apr-98 1:46PM

Date / Class # / Notes
Jan 6, T / No Labs
7, W / 1 / HW #1 Assigned / No Labs
Lab 1 Assigned
8, R
9, F / 2
12, M / 3 / Lab 1 Starts
13, T / Lab 1
14, W / 4 / HW #1 Due(M)/ HW #2 Assigned
Lab 1 / Lab 2 Assigned
15, R / Lab 1
16, F / 5
19, M / MLK HOLIDAY
No Labs or Classes
20, T / No Labs
21, W / 6 / HW #2 Due(S)/ HW #3 Assigned
Lab 2 Starts/ Lab 3 Assigned
22, R
23, F / 7
26, M / 8 / Lab 2
27, T / Lab 2
28, W / 9 / Lab 3 Starts
29, R
20, F / 10 / HW #4 Assigned
Feb 2, M / 11 / HW #3 Due(B)/ Lab 3
3, T / Lab 3
4, W / 12 / Lab 4 Assigned / No Lab
5, R
6, F / 13 / EXAM #1 / No Lab
9, M / 14 / Lab 5 Assigned
10, T / Lab 4 Starts
11, W / 15 / HW #4 Due(M)/ Lab 4
12, R
13, F / 16 / HW #5 Assigned
16, M / 17 / Lab 4
17, T / Lab 5 Starts
18, W / 18 / Lab 5 / Lab 6 Assigned
19, R
20, F / 19
23, M / 20 / Lab 5
24, T / No Labs
25, W / 21 / HW #5 Due(S)
Lab 6 Starts
26, R
27, F / 22
Date / Class # / Notes
Mar 2, M / 23 / Lab 6 / Lab 7 Assigned
3, T / Lab 6
4, W / 24
5, R
6, F / 25
9-13, M-F / SPRING BREAK
No Labs or Classes
16, M / 26 / Lab 7 Starts
17, T / Lab 7
18, W / 27 / Lab 7 / Lab 8 Assigned
19, R
20, F / 28 / HW #6 Assigned
23, M / 29 / EXAM #2
No Lab
24, T
25, W / 30 / Lab 9 Assigned
26, R
27, F / 31
30, M / 32 / HW #6 Due (B)
31, T / Lab 8 Starts
Apr 1, W / 33 / Lab 8
2, R
3, F / 34 / HW #7 Assigned
6, M / 35 / Lab 8
7, T / Lab 9 Starts
8, W / 36 / Lab 9
9, R
10, F / 37 / Lab 10 Assigned
13, M / 38 / HW #7 Due(M)/ Lab 9
14, T / No Labs
15, W / 39 / EXAM #3 / No Labs
16, R
17, F / 40
20, M / 41 / Lab 10 Starts
21, T / Lab 10
22, W / 42 / Lab 10
28, Tues / FINAL EXAM
5:30pm-7:30pm in NEB 100

University of FloridaEEL 4712 Spring 1998Dr. Eric M. Schwartz

Department of Electrical & Computer EngineeringProfessor in ECE

Page 1/4SYLLABUS22-Apr-98 1:46PM

Day of First Labs

Monday / Tuesday / Wednesday
1, 7, 10 / 4, 5, 8, 9 / 2, 3, 6

Probable Lab Topics:

University of FloridaEEL 4712 Spring 1998Dr. Eric M. Schwartz

Department of Electrical & Computer EngineeringProfessor in ECE

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  • Lab 1Cascading Synchronous Counters(B)
  • Lab 2Introduction to VHDL(B)
  • Lab 3PALs to replace MSI(B)
  • Lab 4ALU(B)
  • Lab 5State Machine Introduction(B)
  • Lab 6:Keypad Scanner(B)
  • Lab 7A/D(B)
  • Lab 8Asynch. Parallel-Serial Receiver(B)
  • Lab 9Serial Transmitter with Multiplier (B)
  • Lab 10:Waveform Generator (B)

University of FloridaEEL 4712 Spring 1998Dr. Eric M. Schwartz

Department of Electrical & Computer EngineeringProfessor in ECE

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Major Course Topics (in no particular order):

University of FloridaEEL 4712 Spring 1998Dr. Eric M. Schwartz

Department of Electrical & Computer EngineeringProfessor in ECE

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  • Mixed Logic (Direct Polarity Indication)
  • SOP, POS, Truth Tables, K-Maps
  • Array Logic: PLDs, PALs, PLAs
  • Counters, Encoders, 7-Segment Displays
  • Adders: FA, HA, Carry Look-Ahead
  • Other MSI: (Multiplexer, DeMux, Decoder, etc.)
  • Flip-Flop, Register
  • Shift Register, RAM, ROM, EPROM, EEPROM
  • Address Decoding
  • ROMs for Logic
  • Timing and Hazards (function and logic)
  • Propagation Delay
  • VHDL!VHDL!VHDL!
  • PAL Specs
  • ALU
  • Synchronous Machines, FSMs, ASMs
  • Counters, Sequencers
  • Moore and Mealy Machines
  • Keypad Controllers
  • Logic State Analyzer
  • To use state assignment or not to state assignment, that is the question.
  • State Machines and S-R Flip Flops
  • D/A, A/D, Successive Approximation Controller
  • Multipliers
  • Asynchronous Serial to Parallel Converter
  • RS-232
  • LogicWorks™
  • Waveform Generator
  • S-Records
  • TTL Specs and Timing Diagrams
  • CMOS, ECL Specs
  • Interfacing TTL, CMOS, and ECL
  • Asynchronous Design

University of FloridaEEL 4712 Spring 1998Dr. Eric M. Schwartz

Department of Electrical & Computer EngineeringProfessor in ECE

Page 1/4SYLLABUS22-Apr-98 1:46PM