BUILT-IN RESEEDING WITH MODIFYING TECHNIQUE FOR BIST
Jiann-Chyi Rau, Ta-Wei Yang, Ying-Fu Ho
Department of Electrical Engineering, Tamkang University
151, Ying-Chuan Rd. Tamsui, Taipei Hsien 251
Taiwan, R.O.C
Abstract: - During built-in self-test (BIST), the set of patterns generated by a pseudo-random patterns generator may not provide a sufficiently high fault coverage and many patterns was undetected fault so some patterns not make test time can decrease. In this paper, we reseed and modify the pseudo-random bit to improve test length and achieve fault coverage of 100%. The fact that a random test set contains useless (non fault dropping) patterns, so we use parallel technology, including both reseeding and bit modifying (also called pattern mapping) to remove useless patterns (i.e. reduce the test time), leading to very short test length. The technique we present is applicable for single-stuck-at faults. Experimental results indicate that complete fault coverage-100% can be obtained with decrease test time.
Key-Words: BIST, pseudo-random patterns, reseed and modify, test length, single-stuck-at faults, fault coverage
1 Introduction
Modern design and package technologies make external testing increasingly difficult and the built-in self test (BIST) has emerged as a promising solution to the VLSI testing problem. BIST is a design for testability methodology aimed at detecting faulty components in a system by incorporating test logic on-chip. The main components of a BIST scheme are the test pattern generator (TPG), the response compactor, and the signature analyzer. The test generator applies a sequence of patterns to the circuit under test (CUT), the response are compacted into a signature by the response compactor, and the signature is compared to a fault-free reference value.
Many digital circuit contain random-pattern-resistant (r.p.r) faults that limit the coverage of pseudo-random testing [5]. The r.p.r faults are faults with low detectability (Few patterns detect them). Several techniques have been suggested for enhancing the fault coverage achieved with BIST. These techniques can be classified as:(1) Modifying the circuit under test (CUT) by test point insertion [5][15], or by redesigning the CUT [13][4], to improve the fault detection probabilities. (2) Weighted pseudo-random patterns, where the random patterns are biased using extra logic to increase the probability of detecting r.p.r fault [6]. (3) Mixed-mode testing where the circuit is tested in two phases. In the first phase, pseudo-random patterns are applied. In the second phase, deterministic patterns are applied to target the undetected faults [8][16].
Figure.1 It is show that by performing parallel global operations. This paper presents a new mixed-mode approach in which deterministic test cubes are embedded in the pseudo-random sequence of bits. Logic is added at the serial output of the LFSR to modify the pseudo-random bit sequence so that it contains patterns that detect the r.p.r faults. This is accomplished by “inversion” certain bits in the sequence. A procedure is described for designing the modifying-bit sequence generator in a way that decrease test length and area overhead with obtain high fault coverage. The new test-per-scan BIST scheme presented in this paper is sort of a hybrid approach. We modify test-per-scan architecture was due to addition modifying circuit. It is different from weighted pattern testing because it is not based on probability. It guarantees that certain test cube will be applied to the circuit-under-test during a specified test length.
The scheme presented in this paper is also different from previous mixed-mode schemes for test-per-scan BIST. In the proposed scheme, no pattern is stored in a ROM, and that use fewer number of test length and seed can achieve desire high fault coverage.
Figure.1: Block Diagram for parallel Generation
of useful patterns
The paper is organized as follows. Section 2 introduces the related literature. Section 3 describes the modifying-bit architecture and the procedure for designing the modifying-bit sequence generator is presented. Section 4 shows the simulation results and Sec. 5 concludes the paper.
2 Related work
In a “test-per-scan” scheme do not affect the system behavior so much, as only a scan chain is included in the mission logic. The deterministic patterns (also called seeds) are applied after a random test to reduce the number of patterns, deterministic patterns are loaded into the LFSR and then expended into the desired patterns in the scan chain.
In [14], their technique, random patterns that don’t detect r.p.r faults are mapped to ATPG generated cubes through combinational logic. The mapping is performed in two step, the pseudo-random patterns are indentified in the first step, and the ATPG cubes are loaded in the second step. Several iterative minimization heuristics are applied to reduce the area overhead of the mapping logic.
[12] presented a reseeding-based technique that improves the encoding efficiency by using variable-length seeds together with a multiple polynomial LFSR. The technique reuses part of the scan chain flip-flop in expanding the seeds.
In [1], their technique is based on deterministic seeds which expand into ATPG patterns so 100% fault coverage can be achieved. The new seed is loaded by putting the LFSR in the state that precedes the seed value, so that at the next clock pulse, the new seed is in the LFSR. In their technique, first, generate ATPG patterns for faults that were not detected with pseudo-random patterns and calculate seeds for these patterns. Second, when a seed is loaded into the LFSR, let the LFSR run in autonomous mode for sometime because there is a chance that some of the ATPG patterns will drop more faults so that some of the ATPG patterns are not needed. Third, as long as pseudo-random patterns don’t detect faults, the LFSR should be loaded with a new pattern. Figure.2(a) show the structure of the reseeding circuit.
The above scheme have the advantage. They also have the advantage of not requiring seed storage, However, they use seeds that don’t particularly target undetected faults or increase test length. Our technique is based on useful (fault dropping) patterns which expand into ATPG patterns so reduced the test length and high fault coverage can be achieved.
2.1 Built-In Reseeding logic
In their technique, built-in reseeding [1] (encoding the seeds in hardware) refers to loading the PRPG with a seed that expands into a precomputed test pattern. Their technique use muxed flip-flop as shown in figure.2(a). By activating the select line of a given mux, the logic value in the corresponding LFSR stage is inverted and that applies pseudorandom patterns between the deterministic seeds because there is a chance more faults will be detected. Once it is time for reseeding, a new seed is loaded by putting the LFSR in the state that precedes the seed value, so that at the next clock pulse, the new seed is in the LFSR, and then goes back to the autonomous mode and so on and so forth until the detecting more r.p.r faults and desired coverage achieved.
Figure.2: (a) 4-stage LFSR with reseeding circuit
(b) 4-stage reseeding with modifying circuit.
3 Modifying-Bit Architecture
The ATPG generate test cubes are embedded in a way that guarantees that faults are currently detected after the test cubes are embedded. This is performed by modified patterns that don’t drop any faults. As long as the patterns can be reduce faults, then we would not modify pattern. High fault coverage can obtained by change some bit of undetected patterns.
In order to reduce the Modify-Bit Logic, it is the most significant to choose a set of patterns that don’t decrease any faults (i.e., useless patterns) in the circuit-under-test.
In order to easy to decode so we must be to choose a set of patterns by compare number of inverse bit useless patterns with test cubes, and that pick out pattern of the fewer number of different bit from all test cubes.
Figure.3: Example modifying with reseeding circuit
When constructing the bit counter, the states of the bit counter can be decoded by simply using n-input AND gates where n is equal to the number of bits in the bit counter as shown in Figure.3. The number of bit counter depend on length of the scan chain.
In new BIST architecture, a bit counter function used to choose when to bit value of LFSR shift into the scan chain; meanwhile, check on position of the different bits values the correlation between useless pattern and test cube. Our technique is based on modify some bits on useless patterns of pseudorandom mode so can shortens the test length; and further, it is decrease number of seeds. The Modify Bit Logic (MBL) block is shown in Figure.3. The MBL block illustrated use three AND gates instead of modify one bit, and therefore 3k (total amount of modify bits for k) indicates total hardware of MBL, yet we use synthesizer given hardware less than 3k. Thus our technique pay the price in hardware overhead, so as to high fault coverage can be achieved and decrease number of test length with seeds.
3.1 Obtaining Test Cubes and Embedding
For a start, the step is to simulate the n-state LFSR for the given test length L to determine the set of pseudorandom patterns that are applied to the circuit-under-test. For each of the L patterns that are generated. Fault simulation is then performed on the CUT for the pseudorandom patterns to see which faults are detected and which are not. The faults
Figure.4: Example modifying-bit and reseeding
that are not detected are the faults that require modifying of pseudorandom bit sequence.
Figure.4 show the example will be used to illustrate the procedure described in this paper. For example, the test cube c_4 (0111), is considered in the 3rd bit position. That is because other of the specified bits in 1st, 2nd, and 4th bit positions are the same as pseudorandom pattern c_10 (undetected fault pattern) and so inversion 3rd bit position of c_10 at pseudorandom sequence of bits that is shifted into the scan chain in order to embed deterministic test cube in the sequence.
In this paper, we present is based on the following steps:
Step 1: First, the test cubes generated by ATPG tool and calculated the position (clock cycle) of the ATPG cube run in pseudorandom mode.
We must found out ATPG patterns was centered on the Nth cycle of pseudorandom mode, so that can chose suitable for the seed and then embedded into the LFSR (overwrite the original pseudorandom patterns).
Step 2: We must considering the waste of cycle (i.e., position of useless patterns) between the useful patterns at run pseudorandom mode. That is because position of useless patterns will be overwritten by test cubes (i.e., change some bits).
As long as pseudorandom patterns don’t drop faults, the seed should loaded into the LFSR [1], yet the seed loaded into the LFSR that could be skipping some useful patterns, and therefore must be regenerate those patterns.
Step 3: The useless patterns of the LFSR run in autonomous mode as compare with ATPG test cubes, and count number of different bits position and pick out number of different less bit from all test cubes.
In accordance with those bits are different and then done inversion changes. In the step, two primary cause for modify become useful patterns so that could be detected more faults and minimize hardware area for another.
Step 4: According to step 3, we can obtain a useful pattern, and then modify those position of reversed bit value (inversion the reversed bits) at pseudorandom sequence of bits that is shifted into the scan chain.
The purpose is modifying some bits at the same time the bits was also shifted into the scan chain. Figure.4 show the example of modify (i.e., inverse of some bits) some bits and reseeding, so that can obtain desired patterns and detecting more faults.
Step 5: Lastly, if all ATPG test cubes whole appeared on pseudorandom mode, no other than, all test cubes that are embedded. Otherwise, loop back to step 3.
The modifying-bit generator is designed so that when the pseudorandom patterns undetected faults that are altered to embed test cube are added to the set of patterns that drop faults.
Figure.5 shows where the reseeding and modifying circuit suit in a system level view of a circuit with an LBIST controller. The pattern counter is used to count the patterns and bit counter is used to count the bits of pattern applied to the circuit under test. Complete details about the architecture for built-in reseeding are given are in [1].
Figure.5: Modifying with Reseeding circuit in a system view of BIST environment
In a BIST environment, where the LFSR is known in advance and the initial seed and test length by ATPG tool generation test cubes, the reseeding and modifying circuit may take its inputs form the pattern counter instead of the LFSR contents. The modifying circuit requires counting for certain bits of change in the sequence so modifying circuit may take its inputs form the bit counter.
4 Simulation Results
In this section we present the results of some simulation experiments. We performed our experiments on some of the ISCAS 89 benchmarks. The characteristics of the benchmarks we used are shown in Table 1. The table shows the number of primary input, number of faults, total amount of modify bits and flip-flop in the scan chain. The BC column lists the sizes of the bit counters. The number of changing bits determines the area of the modifying circuit. It also shows the number of gate count of the circuit.
In our technique, deterministic test cubes were generated using the ATPG tool of the SIS.
Table 1: ISCAS 89 CUTs Used in the Experiments
4.1 Comparison with Experimental Results
We performed some simulation experiments to compare our technique with [7]. The reseeding with modifying-bit generators were designed to provide 100% fault coverage of all detectable single stuck-at faults for a test length of fewer patterns.
The experiment was designed such that pseudorandom patterns are applied first. Then, test patterns are generated and the seeds are calculated, and that the technique includes modifying-bit from the test patterns.