Time-voltage output:
REPORT :
T-Spice - Tanner SPICE
Version 13.00
Standalone hardware lock
Product Release ID: T-Spice Win32 13.00.20080321.01:01:33
Copyright © 1993-2008 Tanner EDA
Opening output file "C:\Documents and Settings\Zebros-004\My Documents\Tanner EDA\Tanner Tools v13.0\S-Edit\pll_test\self-healing circuit\pll.out"
Parsing "C:\Documents and Settings\Zebros-004\My Documents\Tanner EDA\Tanner Tools v13.0\S-Edit\pll_test\self-healing circuit\pll.spc"
Initializing parser from header file "C:\Documents and Settings\Zebros-004\My Documents\Tanner EDA\Tanner Tools v13.0\S-Edit\pll_test\self-healing circuit\header.sp"
Including "F:\ABI\tanner\Tanner EDA\Model files\IBM013.md"
Loaded BSIM3v31 model library, Berkeley BSIM3 VERSION 3.1 with extensions
Accuracy and Convergence options:
numndset|dchold = 100 vmax = 0 [V]
Timestep and Integration options:
relq|relchgtol = 0.0005
Model Evaluation options:
dcap = 2 defnrb = 0 [sq] defnrd = 0 [sq]
defnrs = 0 [sq] tnom = 25 [deg C]
General options:
search = C:\Documents and Settings\Zebros-004\My Documents\Tanner EDA\Tanner Tools v13.0\Libraries\Models
temp = 25 [deg C] threads = 2
Output options:
acout = 1 ingold = 0
Device and node counts:
MOSFETs - 1275 MOSFET geometries - 16
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 4 Resistors - 7
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 5 Current sources - 2
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 External C model instances - 0
HDL devices - 0
Subcircuits - 0 Subcircuit instances - 306
Independent nodes - 674 Boundary nodes - 6
Total nodes - 680
Parsing 0.01 seconds
Setup 0.20 seconds
DC operating point 0.33 seconds
Transient Analysis 32.44 seconds
Overhead 1.45 seconds
------
Total 34.44 seconds
Simulation completed
Netlist:
* SPICE export by: SEDIT 13.00
* Export time: Mon Mar 03 15:49:21 2014
* Design: self-healing circuit
* Cell: pll
* View: view0
* Export as: top-level cell
* Export mode: hierarchical
* Exclude .model: yes
* Exclude .end: no
* Expand paths: yes
* Wrap lines: 80 characters
* Root path: C:\Documents and Settings\Zebros-004\My Documents\Tanner EDA\Tanner Tools v13.0\S-Edit\pll_test\self-healing circuit
* Exclude global pins: no
* Control property name: SPICE
********* Simulation Settings - General section *********
.include "F:\ABI\tanner\Tanner EDA\Model files\IBM013.md"
*************** Subcircuits *****************
.subckt Buf1 In Out Gnd Vdd
*------Devices: SPICE.ORDER < 0 ------
* Design: LogicGates / Cell: Buf1 / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: 1x Buffer
* Date: 6/14/2007 1:47:11 AM
* Revision: 33
*------Devices: SPICE.ORDER > 0 ------
MN1 1 In Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN2 Out 1 Gnd Gnd NMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u
MP1 1 In Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u
MP2 Out 1 Vdd Vdd PMOS W=2.5u L=250n M=4 AS=7.625p PS=21.1u AD=6.25p PD=15u
.ends
.subckt DFFC ClB Clk Data Q QB Gnd Vdd
*------Devices: SPICE.ORDER < 0 ------
* Design: LogicGates / Cell: DFFC / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: D Flip-Flop with Clear
* Date: 6/12/2007 1:09:34 AM
* Revision: 43
* Design: LogicGates / Cell: DFFC / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: D Flip-Flop with Clear
* Date: 6/12/2007 1:09:34 AM
* Revision: 43
*------Devices: SPICE.ORDER > 0 ------
MN1 5 Data Gnd 0 NMOS W=1.9u L=250n AS=1.71p PS=5.6u AD=1.71p PD=5.6u
MN2 4 CB 5 0 NMOS W=1.9u L=250n AS=1.71p PS=5.6u AD=1.71p PD=5.6u
MN3 7 10 8 0 NMOS W=1.9u L=250n AS=1.71p PS=5.6u AD=1.71p PD=5.6u
MN4 4 C 7 0 NMOS W=1.9u L=250n AS=1.71p PS=5.6u AD=1.71p PD=5.6u
MN27 14 Q Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN11 CB Clk Gnd 0 NMOS W=1u L=250n AS=900f PS=3.8u AD=900f PD=3.8u
MN12 C CB Gnd 0 NMOS W=1u L=250n AS=900f PS=3.8u AD=900f PD=3.8u
MN13 8 ClB Gnd 0 NMOS W=1.9u L=250n AS=1.71p PS=5.6u AD=1.71p PD=5.6u
MN14 10 4 Gnd 0 NMOS W=1.9u L=250n AS=1.71p PS=5.6u AD=1.71p PD=5.6u
MN15 Q 12 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN16 12 CB QB 0 NMOS W=1.9u L=250n AS=1.71p PS=5.6u AD=1.71p PD=5.6u
MN17 QB ClB 14 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN18 12 C 13 0 NMOS W=1.9u L=250n AS=1.71p PS=5.6u AD=1.71p PD=5.6u
MN19 13 10 Gnd 0 NMOS W=1.9u L=250n AS=1.71p PS=5.6u AD=1.71p PD=5.6u
MP1 4 C 3 Vdd PMOS W=2.15u L=250n AS=1.935p PS=6.1u AD=1.935p PD=6.1u
MP2 3 Data Vdd Vdd PMOS W=2.15u L=250n AS=1.935p PS=6.1u AD=1.935p PD=6.1u
MP3 4 CB 6 Vdd PMOS W=1.75u L=250n AS=1.575p PS=5.3u AD=1.575p PD=5.3u
MP11 CB Clk Vdd Vdd PMOS W=1u L=250n AS=900f PS=3.8u AD=900f PD=3.8u
MP4 6 10 Vdd Vdd PMOS W=1.75u L=250n AS=1.575p PS=5.3u AD=1.575p PD=5.3u
MP12 C CB Vdd Vdd PMOS W=1u L=250n AS=900f PS=3.8u AD=900f PD=3.8u
MP13 4 CB 9 Vdd PMOS W=1.4u L=250n AS=1.26p PS=4.6u AD=1.26p PD=4.6u
MP14 10 4 Vdd Vdd PMOS W=1.9u L=250n AS=1.71p PS=5.6u AD=1.71p PD=5.6u
MP17 Q 12 Vdd Vdd PMOS W=3.4u L=250n AS=3.06p PS=8.6u AD=3.06p PD=8.6u
MP9 9 ClB Vdd Vdd PMOS W=1.5u L=250n AS=1.35p PS=4.8u AD=1.35p PD=4.8u
MP22 QB Q Vdd Vdd PMOS W=3u L=250n AS=2.7p PS=7.8u AD=2.7p PD=7.8u
MP26 12 CB 11 Vdd PMOS W=2u L=250n AS=1.8p PS=5.8u AD=1.8p PD=5.8u
MP27 11 10 Vdd Vdd PMOS W=2u L=250n AS=1.8p PS=5.8u AD=1.8p PD=5.8u
MP28 12 C QB Vdd PMOS W=2u L=250n AS=1.8p PS=5.8u AD=1.8p PD=5.8u
MP29 QB ClB Vdd Vdd PMOS W=3u L=250n AS=2.7p PS=7.8u AD=2.7p PD=7.8u
.ends
.subckt INV A Out Gnd Vdd
*------Devices: SPICE.ORDER < 0 ------
* Design: LogicGates / Cell: INV / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: Inverter
* Date: 6/14/2007 1:47:11 AM
* Revision: 64
*------Devices: SPICE.ORDER > 0 ------
MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u
.ends
.subckt Mux2 A B Out Sel Gnd Vdd
*------Devices: SPICE.ORDER < 0 ------
* Design: LogicGates / Cell: Mux2 / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: 2 Input Multiplexer
* Date: 5/22/2007 12:13:54 AM
* Revision: 37
*------Devices: SPICE.ORDER > 0 ------
MN5 6 G Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN6 Out 3 Gnd 0 NMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u
MN1 G Sel Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN2 3 A 4 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN3 4 Sel Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN4 3 B 6 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 G Sel Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP2 2 G Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP3 3 A 2 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP4 5 Sel Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP5 3 B 5 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP6 Out 3 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u
.ends
.subckt NAND2C A B Out1 Out2 Gnd Vdd
*------Devices: SPICE.ORDER < 0 ------
* Design: LogicGates / Cell: NAND2C / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: 2 Input NAND with complementary output.
* Date: 6/14/2007 1:47:11 AM
* Revision: 62
*------Devices: SPICE.ORDER > 0 ------
MN1 Out1 A 1 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN2 1 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN3 Out2 Out1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u
MP2 Out1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u
MP3 Out2 Out1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u
.ends
.subckt NOR2 A B Out Gnd Vdd
*------Devices: SPICE.ORDER < 0 ------
* Design: LogicGates / Cell: NOR2 / View: Main / Page:
* Designed by: Tanner EDA Library Development Team
* Organization: Tanner EDA - Tanner Research, Inc.
* Info: 2 Input NOR
* Date: 7/13/2007 12:54:48 AM
* Revision: 33
*------Devices: SPICE.ORDER > 0 ------
MN1 Out B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MN2 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MP1 Out B 1 Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u
MP2 1 A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u
.ends
.subckt NOR2C A B Out1 Out2 Gnd Vdd
*------Devices: SPICE.ORDER < 0 ------
* Design: LogicGates / Cell: NOR2C / View: Main / Page:
* Designed by: Author
* Organization: Organization
* Info: Info
* Date: 7/13/2007 1:14:17 AM
* Revision: 16
*------Devices: SPICE.ORDER > 0 ------
MMN1 Out1 A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MMN2 Out1 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MMN3 Out2 Out1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MMP1 1 B Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u
MMP2 Out1 A 1 Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u
MMP3 Out2 Out1 Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u
.ends
.subckt bottom0level0detector In Q2 Gnd Vdd
*------Devices: SPICE.ORDER == 0 ------
XNOR2_1 N_8 N_9 N_7 Gnd Vdd NOR2
XINV_1 N_4 N_8 Gnd Vdd INV
XINV_2 N_6 N_9 Gnd Vdd INV
XINV_3 N_15 N_11 Gnd Vdd INV
XINV_4 N_18 N_27 Gnd Vdd INV
XINV_5 N_21 N_28 Gnd Vdd INV
XDFFC_1 Vdd N_11 Vdd N_12 N_29 Gnd Vdd DFFC
XDFFC_2 N_12 N_11 Vdd Q2 N_30 Gnd Vdd DFFC
*------Devices: SPICE.ORDER > 0 ------
CCapacitor_1 N_10 Gnd 1p
CCapacitor_2 N_19 N_27 1p
RResistor_2 In N_19 R=10k
RResistor_3 N_19 N_25 R=10k
RResistor_4 N_26 N_28 R=10k
RResistor_5 N_24 N_28 R=10k
RResistor_6 N_24 Gnd R=10k
RResistor In N_17 R=10k
MNMOS_1 N_2 N_2 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 N_4 N_2 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_3 N_1 N_1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_4 N_6 N_1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_5 N_10 N_7 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_6 N_15 N_13 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_7 N_13 N_13 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_8 N_18 N_20 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_9 N_20 N_20 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_10 N_22 N_22 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_11 N_21 N_22 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS N_25 N_26 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_10 N_13 N_31 N_14 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_11 N_18 N_17 N_16 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_12 N_20 N_19 N_16 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_13 N_16 N_20 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_14 N_23 N_22 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_15 N_22 N_27 N_23 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_16 N_21 N_24 N_23 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 N_3 N_2 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_2 N_2 N_27 N_3 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_3 N_4 N_28 N_3 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_4 N_5 N_1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_5 N_1 N_10 N_5 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_6 N_6 N_28 N_5 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_7 N_10 N_7 Vdd N_7 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_8 N_14 N_13 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_9 N_15 N_10 N_14 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 N_31 Gnd PULSE(0 5 0 5n 5n 95n 200n)
.ends
.subckt dff CLK D Q Qbar Gnd Vdd
*------Devices: SPICE.ORDER == 0 ------
XINV_1 N_1 N_6 Gnd Vdd INV
XINV_2 Qbar Q Gnd Vdd INV
*------Devices: SPICE.ORDER > 0 ------
MNMOS_1 N_3 N_1 N_5 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 Qbar N_6 N_7 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_3 N_7 CLK Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_4 N_5 CLK Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_5 N_1 D Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 N_1 CLK Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_2 N_3 CLK Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_3 Qbar N_3 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
.ends
.subckt PFD CLKout CLKref DOWN UP Gnd Vdd
*------Devices: SPICE.ORDER == 0 ------
XINV_1 N_5 UP Gnd Vdd INV
XINV_2 N_9 DOWN Gnd Vdd INV
XNOR2_1 N_9 N_5 N_1 Gnd Vdd NOR2
XBuf1_1 CLKref N_3 Gnd Vdd Buf1
XBuf1_2 CLKout N_8 Gnd Vdd Buf1
*------Devices: SPICE.ORDER > 0 ------
MNMOS_1 N_4 N_1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 N_5 CLKref N_6 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_3 N_6 N_4 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_4 N_7 N_1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_5 N_10 N_7 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_6 N_9 CLKout N_10 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_7 N_5 N_3 N_6 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_8 N_9 N_8 N_10 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 N_2 N_1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u