Time Allocation & Sequence of Lectures

Time Allocation & Sequence of Lectures

Approximate Date / Topics / Text Reading

PART-I

1. Introduction to FPGA’s and ASIC Design

Week # 1&2 / Introduction / Chp. 1
Overview of FPGA
Hardware Description Languages (HDL)
Design Automation Tools

2. Introduction to VHDL

Week #3
/ Design Abstraction Level / Chp. 2
Behavioral ,gate ,transistor, data flow ,structure
Example of 2-to-1 Mux
Synthesis and simulation( Test Benches)
3. Logical Control Structure
Week #4&5 / Logical \Arithmetic Operations / Chp. 4
Logic Control Structure
Control Structure in VHDL

4. Combinational Logic in VHDL

Week #6 / Multiplexers / Chp. 6
Encoders
decoders
Comparators
Synthesis of Combinational Logic

6. More Combination Logic

Week #7&8 /

Structural BCD to 7 segment Decoder

/ Chp.8
Dataflow BCD to 7 segment Decoder
Behavioral BCD to 7 segment Decoder
Full adder
Carry Look Ahead Adder

Modeling Synchronous Logic Circuits

Week #9&10 / Introduction to Synchronous Logic Circuits
Latches
clocks
D Type Flip Fop
SR Flip Fop
Using Synchronous Logic Circuits
Week #10&11 / Standard Sequential Components
Registers
Counters
Different types of counters

Memories in VHDL

Week #11&12 / Introduction to memories
Latches
clocks
D Type Flip Fop
SR Flip Fop
Finite State Machine (FSM)
Week #13&14 / State Diagrams
Analysis of Moores FSM
Analysis of Mealy FSM
FSM Configuration
General Purpose Microprocessors
Week
#14&15 / Overview of the CPU design
Construction of a Dedicated Microprocessors
VHDL for Dedicated Microprocessor
VHDL for General Purpose Microprocessors