IEEE NSS2002 submission abstract/summary

The first integration test of the ATLAS end-cap muon level 1 trigger system

K.Hasuko, H.Kano, T.Maeno,Y.Matsumoto, Y.Nakamura, H.Sakamoto ,

C.Fukunaga, Y.Ishida, S.Komatsu,K.Tanaka,

M.Ikeno,K.Nakayoshi,O.Sasaki ,Y.Yasu

M.Totsuka, Y.Hasegawa,

K.Mizouchi, S.Tsuji,

R.Ichimiya, H.Kurashige,

L.Levinson, D.Lellouch,

N.Lupu,S.Tarem

[Abstract]

The ATLAS end-cap muon level-1 trigger electronics group has constructed and setup an integrated test system, which reads out amplified, shaped and discriminated signals of muon chambers (TGC) and produces the level-1 trigger signal. Although the system has been constructed using yet prototype ASICs orelectronics modules, the design scheme of the trigger,readoutas well as control logics applied in the system is the final one. The size is about 1/1000 of the whole number of channels. The purpose to construct the present integrated systemis to confirm the system design even very in detail, and to measure theperformance before the final production of all the ingredients are launched. In this paper we discuss the validity of the logics with the comparison of the simulation results, the latency measurement, long run tests and control system sequences.

The first integration test of theATLAS end-cap muon level 1 trigger system

[Summary] [NSS Technical Topics: Data Acquisition and Data analysis systems]

For nearly five years, the ATLASend-cap muon trigger group has built the level 1 trigger system. The group has concentrated most of this timeon the development of various ICs because it has been envisaged that the system would not fulfil various requirements (for timing and physical space) given to the level 1 muon trigger unless most of the system tasks were implemented into ASICs. Recently the first round of the fabrication of thefull-spec. custom ICshas beenmostlyfinished. We havethen constructed avertically sliced system with 1/1000scale ofmccumulate the readouttects SEUsofthe total oneusing these prototype ASICs in order to confirm validity of the design and actual functionality before we move onto the final production phase.In the presentation we will discuss the evaluation and performance of the sliced system test, which we have accomplished recently.

The sliced system receives muon chamber output signals, makes the level1 trigger decision and readout data driving. Thus all the functionalities required for the Level 1 muon trigger system are more or less implemented into the system, though the number of input channels is about 1/1000 of the full system (256 input channels).

The system consists of three layers. This three layer structure is common for both the trigger and the readout. The first layer makes a trigger for low pT muon tracks (6 GeV/c to 20 GeV/c) aftersynchronization ofinput signals. The pipe line buffer (level 1 buffer) and the derandomizer for the readout are also installed in this layer. The second layer finds higher pT muons (20 GeV/c), and the data concentrators accumulate the data and relay them to the readout driver in the third layer. In the final system, the data concentrator will act as a data concentrator and distributor.The third layer makes three dimensional trigger decisions using both wire and strip trigger signals.The readout driver receives the data from up to 13 data concentrators (two in the present sliced system), and merged them in a buffer for further processing in the next stage.

Two fold control systems are embedded in the present system; one is a detector control system (DCS) based on the CAN bus technology to control and monitor the detector status, to supply calibration pulses, and to configure the front-end ICs, the other one is the FPGA controller. This is used to reload quickly the FPGA firmware information when it detects defects in the FPGA configuration caused by some single event upset phenomena. The FPGA controller can also access the registers in all the ASICs through the JTAG protocol. Thus we have two independent routes for the configuration of the front-end ICs.

In the system we use seven custom ICs mainly for the trigger and control parts in which fast signal processing is required. The R-coincidence logic in the third layer is built in a Xilinx Virtex FPGA. Virtex FPGAs are also actively employed in a readout data concentrator for data transfer protocol processing.The electronics modules used in the second and third layers are all VME-based, and total four VME crates have been used to store all the modules including programmable pattern generator modules, which emulate chamber output signals and are used for supplying input data to the first layer modules. Every VME crate is connected with a PCvia PCI-VME interface of SBS Bit3. The Linux OS is used for the PCs.

A dedicated software system has been developed for the slice system. Since multiple PCs are involved in the systemand each PC has own VME module, we have built a distributed control system based on the CORBA model in order any PCto control any modules with regardless of local or remote VME access. The control of the FPGA controller and the JTAG protocol handling are also important items for the software system. All the software is written in C++. The object system modeling ismade using UML. Hence an object oriented architecture is consistently implemented in the system.

Information needed for the operation of the system is stored in a database described in XML. The contents are classifiedhierarchically in the order of an electronics module, a chip and its property. If appropriate identifications are given to a module and a chip, all the properties for the target chip are loaded by parsing the XML database.As a GUI chip object window is created during this process, ahuman operator can modify any properties with this window.

In the overall operation of the sliced system, we have checked latency, stability, and consistency with the simulation for the trigger part, and framing and compressing of data for the data concentrators, design validity of the readout driver (bandwidth of an internal bus, software capability of RISC processor embedded, communication of data transfer with the higher level ATLAS DAQ system), and long term tests.

Although the latency allocated for the level1 processing is 2us in order to keep 40MHz rate bunch crossing condition, we have measured actually only as 1.2us. Consistency with the simulation results for input/output combinations is found with trials of more than 13000 input patters. We have to process at least 100KHz level 1 trigger rate for all readout processing. We found that data can be successfully processed with this rate even if all 13 input channels for the readout driver have sensible data

We conclude finally that validation of the design for both trigger and readout for the ATLAS muon end-cap level 1 system will be fine and sufficient for the requirements that the ATLAS collaboration has given.