8-Tap Moving Average Filter
EEL 6323
Eric Donnelly
Jason Liszewski
Scott Owen
Olga Calderon
April 18, 2003
CONTENTS
Abstract...... 4
Introduction...... 4
Project Description…………………………………..... 5
I. System Overview ...... 5
II. Carry Select Adder...... 5
III. Multiplexer ...... 6
IV. Glitch Circuit...... 6
V. Delay Column/Clock…………………………………… 8
Layout Verification………………………………………… 8
Schematics…………………………………………………. 8
Design Scaling……………………………………………… 8
Low Power Features/Power Consumption. ………………. 8
Testing………………………………………………………. 9
Summary……………………………………………………. 10
Appendix...... 11
I. Schematics/Layouts...... 11.1
II.Simulations/Testing Results...... 11.2
III.Floor Plan...... 11.3
Selected Bibliography...... 12
LIST OF ILLUSTRATIONS
I.One-bit Adder Schematic ...... 11.1.a
II.One-bit Adder Layout...... 11.1.b
III. Delay Column Schematic ...... 11.1.c
IV.……………….……………..……Delay Column Layout 11.1.d
V.…………………………………...... Clock Schematic 11.1.e
VI.………………………………………...Clock Layout11.1.f
VII...... Multiplexer Schematic 11.1.g
VIII...... Multiplexer Layout 11.1.h
IX.………………………………..Glitch Circuit Schematic 11.1.i
X.……………………………….….Glitch Circuit Layout 11.1.j
XI. Complete Filter Circuit ...... 11.1.k
XII...... Complete Filter Layout 11.1.l
ABSTRACT
As signals get progressively smaller in devices such as wireless and low voltage systems, the issue of noise becomes a larger problem. This issue is compounded by the increasing speed at which on-chip clocks run. To solve this problem a very fast noise filter is required. One class of these devices is known as the moving average filter. This filter is multiplier free, allowing it to run much faster that conventional digital filters. The moving average filter follows the same architecture of a normal FIR filter, but does not multiply the outputs of each delay register by a coefficient. These filters are often used to filter an incoming signal after an analog to digital conversion, and before a frequency down-conversion. This paper describes the design of an 8-tap, 16-bit moving average filter.
INTRODUCTION
Finite impulse response, (FIR), filters are feed-forward systems that are intrinsically stable, have a simple architecture, and excellent phase management capabilities. A FIR filter has an impulse response that persists for only a finite number of sampled values. The impulse response of an Nth-order FIR filter is given by
h[k] = {h[0],h[1],…,,h[n-1]}
The time-series response of an FIR filter to an arbitrary input x[k] is given by the convolution sum
y[k] =
Graphically then, an eight-tap filter can be shown as
A FIR filter can then be implemented with a shift register array of length N-1, N multipliers—also known as tap weight multipliers—and an accumulator. One of the simplest FIR filters to implement is the moving average filter, since it can be implemented with just shift registers and adders. Mathematically, a MA filter has the transfer function
HMA = (1/N)
In this project we will discuss the basic design of a 16-bit, 8-tap Moving Average filter, including its implementation on a 0.6m CMOS process. We will first discuss the model and its components, then the simulations ran, and its implementation using CADENCE and MATLAB to test the filter. The moving average filter can be used to reduce additive noise from a low frequency signal, as well as smoothening an array of sampled data.
PROJECT DESCRIPTION
SYSTEM OVERVIEW
The moving average filter is made up of two main components: an adder and delay registers. These components can be further broken down in to simpler components. The figure below shows the relation of the main components, with their subcomponents:
Fig.1
Our design objectives are as follow:
- Design a filter that allows the input of 16-bit 2’s complement input signals x[n]
- Use a clocked architecture to synchronize input values and output values
- Store one new input value and produce one output value per clock cycle
- Use 20-bit adders—instead of 16-bit adders—to take care of any possible overflow due to addition
- Give the user the option of using the internal 44.1kHz clock or an external clock of a different frequency
A top-level diagram of the ports on our final design might resemble that of Fig 2.
Fig 2
Pin 1: VDD
Pins 2-17: Input pins x[0] through x[15]
Pins 18-33: Output pins y[0] through y[15]
Pin 34: Chip Select CS
Pin 35: IN_EXT: provides the input for the external clock
Pin 36:EXT_EN: enables the use of the external clock
Pin 37:CLK_OUT: enables to see the output of the clock being used
Pin 38:GND
CARRY SELECT ADDER
As demonstrated in Figure 1, the adder can be broken down into two parts—a full adder and a multiplexer. The adder implemented is a carry select adder. This implies that two adders precompute the sum of the two operands assuming both a carry bit and no carry bit. Then, after the carry bit has been computer from the previous adder, it is used as a select line on a multiplexer to select the correct sum from the two adders. An example of such circuit is shown in Figure 3.
Fig 3
A carry select adder was chosen over other adders for several reasons. It computes two results in parallel, each for different carry assumption—thus making it faster; it uses actual carry in to select correct the result, reduces the delay of the multiplexer, and is fairly power efficient despite its size since there’s a shorter ripple through the adder due to carry.
For this project, we used 20-bit carry select adders to account for any bit overflow that may occur throughout any of the stages. A 16-bit input is fed to the first adder, tying bits[16:19] to the most significant bit. For the last stage, we will have at most, a 19-bit output where the lowest three bits will be dropped and the remaining bits will be send to our output.
MULTIPLEXER
A multiplexer (MUX) is a combinational circuit element that selects data from one of many inputs and directs it to a single output. In this project, the multiplexer is used to select the correct sum and carry in bit for the next stage. The multiplexer consists of pass transistors. The carry out of the previous stage turns on one set of pass transistors allowing the partial sum bits and carry out bit to be passed.
GLITCH CIRCUIT
The glitch circuit consists of a 2-input NAND gate with its output connected to an inverter. It is known that the NAND gate only goes LOW when both inputs are high. The inputs of the NAND gate are connected to an input signal, and the input signal connected through an inverter. The schematic is shown in the Appendix. By sizing the inverter properly (increasing the width of the Polysilicon), when the input signal goes high, the inverted signal stays high for a specific period (determined by the inverter sizing). This means both inputs to the NAND gate are temporarily HIGH, making its output LOW momentarily. After passing this through the final inverter, the final signal is a short pulse. This means that different clock speeds can be used for the chip and the delay buffers will continue to be timed correctly. This signal is scaled for clock distribution.
DELAY COLUMN/CLOCK CIRCUIT
The design that we made allows the user to choose between an internal clock that runs at 44.1kHz, which matches current CD audio sampling specifications, and an external clock that’s enabled through an external enable pin. The internal clock was implemented using eleven CMOS inverters, where the transistors were sized to obtain the desired clock frequency. The delay column in the circuit was implemented using timed buffers that would hold the current value of our output until the next clock cycle. These buffers were implemented using a combination of timed buffers and pass transistors.
LAYOUT VERIFICATION
A 0.6m CMOS process was used to layout the almost 9000 transistors included in the design. CADENCE was used to layout the circuit, and each part of the circuit was layout separately, DRC and LVS checks were ran through each part and, after each part passed the checks, the individual parts were placed together and both checks were ran for the design as a whole.
Our final design passed all the checks successfully, as shown in the si.out file attached in the appendix. The final floor plan of our MA filter design is shown in the appendix. The filter fits into a die size of about [3.2mm x 2.2mm]or 7.04 mm². The appendix will also show the layout of each individual component.
SCHEMATICS
The schematics for the project were also done separately, checked for errors and floating pins, tested, and—once each individual part work—put together using the design hierarchy. The individual schematics for each component are attached as part of our appendix.
DESIGN SCALABILITY
Since each circuit was layout and built separately, the design can be scaled down if the circuit was drawn as one unit at once, instead of different separate parts placed together. Although this would reduce the overall area of the design, implementing it and making sure all the components work and pass all the proper checks would take much longer than using our current approach. Also more taps and adders can easily be added in the empty spaces of the die. More logic can also be added to improve the filter or increase the clock speed.
LOW POWER FEATURES/POWER CONSUMPTION
When designing our filter, several low power features were considered. As mentioned earlier, a carry select adder was chosen since one of its advantages over the ripple propagate adder is that there’s a shorter ripple associated through the adder due to carry and so it saves some power in comparison. Although it does consume more power than other adders, its faster speed is a good tradeoff. Other low power features in our design include the CS pin, which allows the chip to turn off and unable anything from switching since it’s connected to the clock signal.
TESTING
As mentioned earlier, each individual component was tested to ensure its functionality. Below is a breakdown of the tests performed for each unit. These tests can also be used at a production level to verify proper operation. The simulations of these tests are included in the appendix also.
Carry Select One-bit Adder
/Cin / /B / /A / /SUM / /C01 / 0 / 1 / 0 / 1
1 / 0 / 0 / 1 / 0
0 / 0 / 1 / 1 / 0
0 / 0 / 0 / 0 / 0
1 / 1 / 1 / 1 / 1
1 / 1 / 0 / 0 / 1
Multiplexer
A4 / A3 / A2 / A1 / A0 / B4 / B3 / B2 / B1 / B0 / Sel / Q4 / Q3 / Q2 / Q1 / Q00 / 0 / 0 / 0 / 0 / 1 / 1 / 1 / 1 / 1 / 0 / 0 / 0 / 0 / 0 / 0
0 / 0 / 0 / 0 / 0 / 1 / 1 / 1 / 1 / 1 / 1 / 1 / 1 / 1 / 1 / 1
0 / 0 / 0 / 0 / 0 / 1 / 1 / 1 / 1 / 1 / 0 / 0 / 0 / 0 / 0 / 0
Glitch Circuit: To test the glitch circuit, the input signal was set to HIGH and the output pulse was verified.
Final Design
- CADENCE Testing: An impulse response was fed into the filter, and the transient response of the output was observed. The output of the signal should be approximately 0.125 for the first eight outputs and ‘0’ afterwards. After running the simulation, the output value was 0.1249, as shown by bits [18:0] = [0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1].
- MATLAB Testing: The filter was implemented in MATLAB and a noisy input sine wave X was passed through the filter to obtain the output. The filtered output, the noisy input, and the frequency response of the filter were plotted. The MATLAB code used to accomplish this is included in the appendix as well.
SUMMARY
The purpose of this project was to implement a 16-bit 8-tap MA filter, using CADENCE and MATLAB to show its design and functionality. Using a 0.6m CMOS technology, the filter was layout—each component at a time—and ran through DRC and LVS check. Both checks ran successfully for each individual component and for the filter as a whole.
The next task was to verify that all the components worked properly in their schematics. Simulations in CADENCE and MATLAB were performed for the components and the final filter, giving us the desired results. In the final design, we were able to implement a successful MA filter that can be used as a data smoother optimized for the sample frequency of your choice.
BIBLIOGRAPHY
Fred Taylor, The Athena Group, Inc, and Jon Mellot, Hands on Digital Signal Processing, McGraw Hill, 1998
Jan M. Rabaey, Digital Integrated Circuits: A Design Perspective, Prentice Hall, 1996.
Neil H. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, Addison Wesley, 1993
Class Notes, EEL 6323 Advanced VLSI Design, Spring 2003
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