December 30, 2011

ST5000 Video Module

ST5252D

  1. Scope

ST5252D design employs the same features as the previous video modules, ST5252C and earlier models, but includes the ability to add graphics and text superimposed (logically or’d) over the star video image. This will greatly enhance star field identification to the experimenter during flight and ultimately result in more science observation time. Components used are much lower in power and size so as to fit within the existing board dimensions and still not demand more power despite the added features. This PC104 compatible board will plug into the existing stack of ST5K boards with no change to the electrical interface. Due to the complexity, a Xilinx CoolRunner II CPLD is added which requires software from the ST5K processor to control it. This module can operate as previous versions w/o any software control or intervention.

  1. Added Features

Graphics information will be stored in memory mapped 512K RAM. To reduce graphic image jitter, not observe processor updates, there are two 512K GRAPHIC RAMs – GRAMA and GRAMB. The video display will consist of digitized camera data (from VIDEO RAM) and, also, either the graphic data from GRAMA or GRAMB under the control of the ST5K processor. While, say, GRAMA is being displayed GRAMB is being loaded with updated graphics information. After GRAMB is loaded it will be switched to be the display RAM and GRAMA will be available for updates. Writing and reading the GRAMs is the same as RAMA and RAMB camera data in the controller board. GRAM data will be stored in system memory space 0D8000-0DFFFF.

2.1. Registers

There are four registers: Control Status, Bit Plane, Intensity, Memory Page. All registers are Write/Read via I/O commands.

  • Control Status Register – CSR (3 bits) (I/O 130)

The CSR can be written and read by I/O address 130 and data bits 0, 1, 2. CSR(0), CSR(1), CSR(2), respectively.

On power up, the CSR comes up as a logic (0) zero.

CSR(0) disables (logic 0) or enables (logic 1) the graphics memory to be displayed.

CSR(1) disables (logic 1) or enables (logic 0) the display of star video.

CSR(2) displays GRAMA with logic 0 or GRAMB with logic 1. The GRAM that isn’t being displayed is enabled to be written/read by the processor.

  • Bit Plane Register – BPR (8 bits) (I/O 132)

The GRAM is divided into 8 planes. Any combination of planes can be enabled for display. BPR is not reset on power up.

BPR(0) set to “1” allows GRAM(0) to be displayed.

BPR(1) set to “1” allows GRAM(1) to be displayed. Etc.

  • Graphics Intensity Register – GIR (8 bits) (I/O 134)

The intensity of the graphic display can be controlled to 256 levels depending on the contents of the GIR. If the GIR is set to all zeros, the graphics display is set to minimum (zero) intensity. If the GIR is set to all ones, any graphic data bit will be displayed to full intensity. Any combination of GIR bits set between minimum and maximum will result in intensity between minimum and maximum.

GIR is not reset on power up.

  • Graphics Page Register – GPR (4 bits) (I/O 136)

The Graphics memory is directly addressable in 32K blocks. GPR(0)-GPR(3) determines the page to make up the 512K memory. This is the same as RAMA and RAMB in the system controller. GPR is not reset on power up.

2.2.CPLD

The Xilinx Complex Programmable Logic Device (CPLD) contains 90% of the logic required for this board. Once programmed, it will retain its function for 10 years. The schematic (enclosed) is on two sheets. Sheet 1 of 2 is considered the Top Level. Sheet 2 of 2 has most of the logic. Both sheets are divided into functional blocks described below.

2.2.1.Top Level Functional Blocks

Most of the signals that enter or exit the CPLD are shown at this level. Those signals that are inputs must pass through an input buffer, IBUF. Those signals that are outputs must pass through an output buffer, OBUF. These special buffers convert the internal 1.8 volt logic levels to 3.3 volt external levels.

There are seven functional blocks in the Top Level. These are outlined in red and described left to right.

  • INPUT BUFFERS (FROM PC104 BUS)

Shown are A0-A23 and BD0-BD7 inputting the CPLD via IBUFs. There are input examples at this level.

  • VIDEO RAM DATA

These 8 bits of data, VD0-VD7, come from the Video Digital Display unit – the Video RAM output.

  • SHT 2 OF 2 LOGIC SYMBOL

This block, a.k.a., Graphic_RAM_CTLR, describes the I/O signals, the “nets”, that are associated with the second sheet. Some of these are single nets, e.g., BIOWN (Buffered-Input-Output-WriteNegated [logic 0 = true]. Some are bussed – multiple nets, e.g., BA(15:0). [16 nets in this bundle]

  • RESET EXTENSION CKT

This circuit extends the short processor reset pulse several hundred milliseconds by counting the IOWN pulses after the reset pulse. The CPLD reset is extended until 256 IOWN pulses are counted.

  • OUTPUT BUFFERS (TO VDAC)

These are the 8 bits of processed graphic and camera data fed to the display DAC.

  • INPUT BUFFERS (FROM VDAC ADX REG.)

These 18 address signals (VMA0-VMA17) come from the Video Digital Display unit’s address counter and represent the display area in conjunction with the Odd Field Sync (OSYNC) bit. These 19 bits make up the full frame video displayed image.

  • GRAM ADDRESS MULTIPLEXERS

There are two 19 bit address multiplexers. One each for GRAMA and GRAMB.

The inputs to these address multiplexers come from the VDAC ADX REG. (VMA0-VMA17) plus OSYNC to one input. The other input is from the processor address bus A0-A15 plus Page(0)-Page(3) [from sheet 2 of 2]. CSR(2) determines the direction of address control for each GRAM. While one GRAM is being displayed (via VMA0-VMA17 and OSYNC) the other GRAM is being updated by the processor.

2.2.2.Graphic RAM CTLR (Sheet 2 of 2) Functional Blocks

The lower level circuitry is on sheet 2 of 2. There are nine blocks in red described here from left to right.

  • PC GRAM ADX DECODER

This circuit decodes the PC address bus and enables GRAM write/read operations within address space 0D8000 – 0DFFFF as defined by COMP8.

  • PC IO W/R ADX DECODER

This circuit decodes the PC address bus for IO write/read operations at IO addresses 130, 132, 134, 136 as defined by COMP8 and D2_4E (decoder).

  • GRAM A/B DATA W/R CTL

These gates provide the write and read signals for GRAMA and GRAMB. The GRAM that isn’t being displayed will be enabled for write (updating) and read operations as determined by the state of CSR(2).

  • GRAPHIC DATA & VIDEO DATA MIXER

Video data and graphic data are mixed in this block of gates. The 3-input AND gates accept the graphic enable bit, CSR(0), graphic intensity register- GIR (7:0), and the graphic data (single bit) which comes out of the Bit Plane Selector circuit. The 2-input AND gates accept the video data, VD(7:0), and the video enable bit, CSR(1). The 2-input OR gates mix the graphic and video inputs and drive the video DAC inputs.

  • DATA MUX ADX DECODER

The PC104 data multiplexer requires a 3 binary code S0, S1, S2, to select which register or GRAM will be read by the processor. The gates in this block accept inputs from the PC IO W/R ADX DECODER block and GRAM A/B DATA W/R CTL block. See the table on the schematic for more details.

  • BIT PLAN SELECTOR

The 2-input AND gates accept inputs from the GIR and GRAM output data on a bit by bit basis. Example: GD(0) is compared to GIR(0) and both are logic “1” the output of the gate is “1” and that constitutes a graphic data point. The same is true for all the other 7 bit levels. The 8-input OR gate accept the outputs of the 8 AND gates – the output is a “1” if any of the inputs is a “1”.

  • 8 BIT 8 CH. DATA MUX TO PC104 DATA BUS

There are 4 registers and 2 graphic RAMS. The PC can read any of the registers with IOR commands or read either GRAM with MEMR commands. Each data bit comes from an 8-bit wide multiplexer as determined by selector bits S0, S1, S2. The output of the multiplexer is fed to an OBUF8E bus driver. Whenever the DATA MUX ADX DECODER is active it will enable this 8 bit wide bus driver to transfer the multiplexer output to the PC104 bus. Any unused data bits are tied to logic 0 (GND).

  • GRAMA & GRAMB DATA I/O BUFFERS

Each GRAM data port can be written or read back via these 8 bi-directional IOBUFE gates. The GRAMA output bus drivers are enabled by the GRAMA_WRT gate. The GRAMB output drivers are enabled by the GRAMB_WRT gate.

  • GRAM DISPLAY MUX

Both GRAM outputs are fed to a 2-input multiplex. The output of the 8 bit wide multiplexer drives the BIT PLANE SELECTOR. The state of CSR(2) determines which GRAM is selected for display.