Performance Briefs
Intel’s® Performance Acceleration Technology (PAT)
Paul Martin (). Updated 4/18/2003

Summary: Intel’s® Performance Acceleration Technology (PAT) reduces memory access latency in systems based on the Intel® 875P Chipset with 800MHz FSB and 400Mhz DDR RAM. Workstations based on the Intel® 875P typically see a 3% - 7% advantage vs. similar desktop systems based on the Intel® 865G chipset. This is roughly equivalent to one or two processor speed bumps – e.g., 2.6 Ghz or 2.8Ghz -> 3.0Ghz. Applications especially sensitive to memory latency will see the largest improvements.

Background: Performance Acceleration Technology (PAT) is shown here conceptually. The reduced latency path to memory is enabled by using “binned” parts that have faster electrical characteristics.

Results: Two systems were measured – an xw4100 Personal Workstation, and an Intel® 865G-based desktop. Both systems had a 3.0Ghz Pentium 4 CPU, Win2K SP3, 2x512 PC3200 ECC, IDE 7200 RPM, and nVidia Q4 200NVS running at 1280x1024 32 bit, 72 Hz. A variety of tests were run to better cover the space of applications that end users will use. SPECint and SPECfp are groups of tests that represent integer and floating point intensive applications. MCC Winstone consists of a set of multi-media content creation applications. STREAM is a benchmark that measures sustainable memory bandwidth. Monte Carlo is an Excel macro that emulates some financial applications.

Note: Work is currently underway to characterize the impact of PAT in systems running multiple concurrent applications and with systems with Hyper-Threading enabled. This should be complete soon.

Conclusion: PAT improves performance by reducing latency for memory accesses. The performance value depends upon the sensitivity of the benchmark or application to memory latency but typically ranges from 3% - 7%. This is roughly equivalent to the performance obtained by 1 or 2 processor speed bumps.

Links

Intel® 875P Chipset (http://www.intel.com/design/chipsets/875p/?iid=CAHomepage+SpotBot_head&)