4.1
Shannon's Sampling Theorem:
Consider a spectral representation of signal :
Let be bandlimited, and denote the largest F for which , as Fmax.
Theorem: Given Fmax for analog signal , if the sampling frequency Fs is such that:
then can be exactly reconstructed from its sample values using:
where:
and
If the conditions for Shannon’s sampling theorem are violated, then aliasing occurs for all signal components whose frequencies are greater than Fs / 2.
Restate the sampling theorem condition in terms of samples per cycle:
How many samples must be taken within one cycle of the highest frequency component of a signal in order to reconstruct that signal from its samples?
There must be more than 2 samples per cycle.
Sinc function interpolation (ideal low-pass filtering) can be used to compute the exact value of every point between the discrete samples:
Anti-aliasing filter - Typically a low-pass filter is applied to the analog signal before sampling to limit the spectral energy that gets aliased back into the signal spectrum.
Reconstruction filter - A signal can be reconstructed perfectly from its samples through convolution with a Sinc function or filtering with an ideal low-pass filter.
The Analog Interface Circuit (AIC) Chip
- connects to the serial port on the C31
- contains an ADC and a DAC
- contains a switched-capacitor anti-aliasing input filter
- contains a reconstruction output filter
- contains two inputs and one output
- contains a 14-bit ADC and DAC
- programmable sampling rates with a maximum of 20 kHz for maximum performance
- programmable input and out put filters
(The DSK uses the TLC32040 AIC and the EVM uses the TLC32044)
AIC Control
The AIC is controlled through the data transmit register. The two LSBs are used for communication functions. When the two LSBs are zeros, normal transmission occurs, and when they are ones, secondary communication takes place. Secondary communication initializes and controls the AIC, allowing one secondary transmission before switching back.
Master Clock Frequency
MCLK = CLKIN/8 = (50 MHz/8) = 6.25 MHz
Switched Capacity Filter Clock
SCF = MCLK/(2xTA)
Relationship between SCF and filter cutoffs
SCF(required) 288 kHz
------= ------
Fc(desired) 3.6 kHz
Sampling Freqency
Fs = MCLK/(2xTAxTB) (3.3)
Example:
Find proper settings and control words for Fs = 11025 Hz (desired)
Let the cutoff frequency of the input anti-aliasing filter be 4,961 Hz (in general make it 90% of Fs/2).
SCF(required) 288 kHz X (4,961)
------= ------= 396.9 kHz
3.6 kHz
TA = MCLK/(2xSCF) = 6.25 MHz/(2x396.9 kHz) = 7.87 ~= 8 = (00100)b
TB = MCLK/(2xTAxFs) = 6.25 MHz/(2x8x11,025) = 35.43 ~= 35 = (100011)b
The actual SCF is:
SCF = 6.25 MHz/(2xTA) = 390.62 kHz
The actual cutoff frequency or input filter bandwidth is shifted accordingly, or
Fc = 4,961(New SCF/Set SCF) = 4,961(390.62 kHz/396.9 kHz) = 4,882 Hz
The actual sampling frequency is then:
Fs = 6.25 MHz/(2xTAxTB) = 6.25 MHz/(2x8x35) = 11,161 Hz
Bit locations for the control register, and setting TA = RA, with 5 bits for TA, 6 bits for TB, and x for don't care,
0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 ==> 0810h
x x | TA | x x | RA |
Similarly, with TB = RB,
0 1 0 0 0 1 1 0 1 0 0 0 1 1 1 0 ==> 468Eh
x | TB | x | RB |
Utility program AICCALC included with the DSK software tools computes these automatically.
;LOOP.ASM - LOOP PROGRAM. CALLS AICCOM31.ASM
.start ".text",0x809900 ;starting address for text
.start ".data",0x809C00 ;starting address for data
.include "AICCOM31.ASM" ;AIC communication routines
.data ;data section
AICSEC .word 162Ch,1h,4892h,67h ;Fs = 8 kHz
.text ;text section
.entry BEGIN ;start of code
BEGIN LDP AICSEC ;init to data page 128
CALL AICSET ;init AIC
LOOP CALL AICIO_P ;R6 = input, R7 = output
LDI R6,R7 ;output R7=new input in R6
BR LOOP ;loop continuously
.end ;end
*AICCOM31.ASM - AIC COMMUNICATION ROUTINES - POLLING OR INTERRUPT
.data ;assemble into data section
PBASE .word 808000h ;peripheral base address
SETSP .word 0E970300h ;serial port set-up data
ATABLE .word AICSEC ;SP0 AIC init table address
.text ;assemble into text section
AICSET PUSH AR0 ;save AR0
PUSH AR1 ;save AR1
PUSH R0 ;save R0
PUSH R1 ;save R1
LDI @PBASE,AR0 ;AR0 -> 808000h
LDI 1,R0 ;timer CLK=H1/2*(AIC master CLK)
STI R0,*+AR0(28h) ;timer period reg(TCLK0=6.25 MHZ)
LDI 03C1h,R0 ;init timer global register
STI R0,*+AR0(20h) ;reset timer
LDI 62h,IOF ;AIC reset = 0
LDI @ATABLE,AR1 ;AR1 -> AIC init data
RPTS 99 ;repeat next instr 100 times
NOP ;keep IOF low for a while
LDI 131h,R0 ;X & R port control register data
STI R0,*+AR0(42h) ;FSX/DX/CLKX=SP operational pins
STI R0,*+AR0(43h) ;FSR/DR/CLKR=SP operational pins
LDI @SETSP,R0 ;RESET->SP:16 bits,ext clks,std mode
STI R0,*+AR0(40h) ;FSX=output&INT enable SP global reg
LDI 0,R0 ;R0 = 0
STI R0,*+AR0(48h) ;clear serial port XMIT register
OR 06h,IOF ;bring AIC out of reset
LDI 03h,RC ;RC=3 to transmit 4 values
RPTB SECEND ;repeat 4 data transmit of sec com
CALL TWAIT ;wait for data transmit
LDI 03h,R0 ;value for secondary XMIT request
STI R0,*+AR0(48h) ;secondary XMIT request to AIC
CALL TWAIT ;wait for data transmit
LDI *AR1++(1),R0 ;AR1 -> next AIC init data
SECEND STI R0,*+AR0(48h) ;DTR = current AIC data
POP R1 ;restore R1
POP R0 ;restore R0
POP AR1 ;restore AR1
POP AR0 ;restore AR0
RETS ;return from subroutine
AICSET_I ;---CONFIG FOR INTERRUPT ------
CALL AICSET ;call AICSET routine
LDI 0h,IF ;clear IF register
OR 10h,IE ;enable EXINT0 CPU interrupt
OR 2000h,ST ;global interrupt enable
RETS ;return from subroutine
;------TRANSMIT WAIT ROUTINE------
TWAIT PUSH AR0 ;save AR0
PUSH R0 ;save R0
LDI @PBASE,AR0 ;AR0 -> 0808000h
TW1 LDI *+AR0(40h),R0 ;R0=content of SP global control reg
AND 02h,R0 ;see if transmit buffer is ready
BZ TW1 ;if not ready, try again
POP R0 ;restore R0
POP AR0 ;restore AR0
RETS ;return from subroutine
;------AIC TRANSFER ROUTINE------
AICIO_I LDI R7,R6 ;copy output to modify for AIC
LSH 2,R6 ;two LSB must=0 for primary AIC comm
IO PUSH AR0 ;save AR0
LDI @PBASE,AR0 ;AR0 -> 0808000h
STI R6,*+AR0(48h) ;DTR = next data for AIC D/A
LDI *+AR0(4Ch),R6 ;R6 = DRR data from AIC A/D
LSH 16,R6 ;left shift for sign extension
ASH -18,R6 ;right shift keeping sign
POP AR0 ;restore AR0
RETS ;return from subroutine
;------AIC POLLING ROUTINE------
AICIO_P CALL TWAIT ;wait for data to be transferred
CALL AICIO_I ;call AIC transfer routine
RETS ;return from subroutine
SW_IO PUSH AR0 ;save AR0
LDI @PBASE,AR0 ;AR0 -> 0808000h
LDI R7,R6 ;copy output to modify for AIC
LSH 2,R6 ;prepare for secondary AIC com
OR 03h,R6 ;set two LSB for secondary com
CALL TWAIT ;wait for data to be transferred
CALL IO ;call AIC transfer routine
CALL TWAIT ;wait for data to be transferred
STI R1,*+AR0(48h) ;DTR = next data for AIC control
POP AR0 ;restore AR0
RETS ;return from subroutine
;SUBROUTINES FOR PRIMARY OR AUXILIARY INPUT
IOPRI PUSH R1 ;save R1
LDI 063h,R1 ;load secondary com data into R1
CALL SW_IO ;call IO routine to switch inputs
POP R1 ;restore R1
RETS ;return from subroutine
IOAUX PUSH R1 ;save R1
LDI 073h,R1 ;load secondary com data into R1
CALL SW_IO ;call IO routine to switch inputs
POP R1 ;restore R1
RETS ;return from subroutine