Seminar Report’03 Smart Pixel Arrays
INTRODUCTION
High speed smart pixel arrays (SPAs) hold great promise as an enabling technology for board-to-board interconnections in digital systems. SPAs may be considered an extension of a class of optoelectronic components that have existed for over a decade, that of optoelectronic integrated circuits (OEICs). The vast majority of development in OEICs has involved the integration of electronic receivers with optical detectors and electronic drivers with optical sources or modulators. In addition, very little of this development has involved more than a single optical channel. But OEICs have underpinned much of the advancement in serial fiber links. SPAs encompass an extension of these optoelectronic components into arrays in which each element of the array has a signal processing capability. Thus, a SPA may be described as an array of optoelectronic circuits for which each circuit possesses the property of signal processing and, at a minimum, optical input or optical output (most SPAs will have both optical input and output).
The name smart pixel is combination of two ideas, "pixel" is an image processing term denoting a small part, or quantized fragment of an image, the word "smart" is coined from standard electronics and reflects the presence of logic circuits. Together they describe a myriad of devices. These smart pixels can be almost entirely optical in nature, perhaps using the non-linear optical properties of a material to manipulate optical data, or they can be mainly electronic, for instance a photoreceiver coupled with some electronic switching.
Smart pixel arrays for board-to-board optical interconnects may be used for either backplane communications or for distributed board-to-board communications, the latter known as 3-D packaging. The former is seen as the more near-term of the two,
Figure 1
employing free-space optical beams connecting SPAs located on the ends ofprinted circuit boards in place of the current state-of-the-art, multi-level electrical interconnected boards. 3-D systems, on the other hand, are distributed board-to-board optical interconnects, exploiting the third dimension and possiblyemploying holographic interconnect elements to achieve global connectivity(very difficult withelectrical interconnects).
Most work in high speed SPAs has involved the use of either multiple-quantum-well (MQW) modulators or vertical-cavity surface-emitting lasers (VCSELs) as the optical source, and each of these has taken one of two approaches, monolithic and hybrid (e.g., monolithic VCSELs/GaAs and hybrid VCSELs/Si). The hybrid approaches are rapidly gaining popularity since they can take advantage of mainstream silicon microelectronics for the pixel logic circuitry, thereby leveraging the 30 billion dollar silicon semiconductor industry.
LIGHT SOURCE MODULATION USING VCSELs
Figure 2
The figure shows a very simple depiction of a VCSEL showing the substrate, layers of GaAs and AlAs that form the Bragg planes, the quantum well region where gain occurs, the p and n doped regions that make the p.n. diode junction
In a discussion of light source modulated smart pixels, it is necessary to understand the devices that produce the light. The Vertical Cavity Surface Emitting Laser (VCSEL) is a very important and useful light source.
VCSELS utilize a quantum well structure to confine charges to an active region much like edge emitting lasers. The main difference between VCSELS and other semiconductor lasers is the vertical structure. Most semiconductor lasers are planar and emit out of the edge facet on all sides. This configuration allows more active region than in VCSELS. The vertical lasers are constructed from the same planar epitaxy method as the edge emitting lasers, then etch back is used to produce a cylindrical structure. Because the light spends a relatively small amount of time in the gain region, it is necessary to optimize the cavity. Layers are grown such thatthey form Bragg planes so that light with the desired wavelength is preferentially propagated. This structure is illustrated in figure. The VCSEL is crucial to smart pixel applications because of the ability of VCSELS to form two dimensional arrays. They are constructed out of material that is convenient for fabrication of photodetectors and in some cases logic, so, devices like VCSELS and FCSELS can be utilized in monolithic smart pixels.
The VCSEL/Si Smart Pixel Arrays
The VCSEL-based SPAs that will be discussed are hybrid components involving GaAs optoelectronic chips and Si electronic chips. Creating a hybrid Si/GaAs structure involves epitaxially growing GaAs on Si or bonding the two together. Although the former is likely to lead to faster SPAs, it has proven to be a low yield process because of the large lattice mismatch that exists between GaAs and Si, leading to unacceptable GaAs defect levels for fabricating laser diodes. One way to combine the GaAs and Si chips is to mount both onto a common base substrate which can support electrical microstrips between the two chips.
The conventional way of doing this is to bond both to the base substrate with their device sides up and then to electrically connect them by wire bonding both chips to the microstrips and their associated bonding pads on the base substrate. For large array sizes, an unrealistic amount of space on the chips and on the base substrate will be devoted to bonding pads, and the length of the electrical connections between the chips will defeat much, if not all, of the advantage of the optical interconnects. Borrowing a technique from the emerging technology of multi-chip module (MCM) fabrication, the chips can be placed device-side down (called flip-chip) and bump bonded to the carrier. Bump bonding has the distinct advantage that chip connections can be made anywhere on the surface of the chip rather than being confined to the chip's periphery as is the case for wire bonding. This most often leads to a shortening of interconnect lengths, thereby enabling higher speed operation. Furthermore, bump bonding can establish all chip connections in parallel, thus reducing production time for largearrays.Flip-chip bonding of the optoelectronic chip to the base substrate leads to an important constraint on this substrate. Since the optical sources now face the substrate, it must be transparent to permit the optical beams to pass through to the outside of the hybrid structure.
Figure 3.
Glass is the material that can be used due to cost considerations, but the superior thermal properties of sapphire make it very appealing from all but the cost viewpoint. A packaged SPA based on the flip-chip bonding of both the VCSEL array and the electronic array (containing the detectors, processing elements and laser drivers) to a transparent base substrate is shown in figure 3. A hole is drilled in the well of a conventional ceramic package to allow passage of both the incoming and outgoing light beams. Note that the transparent substrate provides a convenient base on which to mount both refractive and diffractive optical devices. Although only shown in the path of the outgoing beams, such beam forming and directing devices could be used in the path of the incoming beams also (e.g., to focus the beams onto the detectors).
SMART PIXEL ARRAY COMPONENTS
The VCSEL chip contains an 8x8 array of top-emitting VCSELs with a 250 µm pitch grown on a GaAs substrate. Each VCSEL consists of a single quantum well active region surrounded by distributed Bragg reflectors, and has been ion implanted for current confinement in the active region. The threshold currents of the VCSELs are between 2.5 and 3.0 mA, the operating currents are less than 8 mA at 2 V, and the output powers are approximately 1 mW. 90 µm square bonding pads for attachment of the flip-chip bonds are evenly interspersed amongst the VCSELs, each pad located a distance of 125 µm (center-to-center) from its associated laser element.The silicon (CMOS) chip contains an 8x8 processing element (PE) array, an 8x8 photoreceiver array, an 8x8 VCSEL driver array, and a 9x15 bonding pad array. Details of the three 8x8 arrays are given in the following paragraphs.
Figure 4.
Each PE is a 1-bit wide processor that can operate at 20 MHz and consists of an arithmetic logic unit, a logic circuit which can perform 16 logic functions, a full adder, a 32-bit shift-register, 6 static registers, and some control circuits. Although the PEs are capable of general purpose processing, they were designed with FFT processing in mind. The PEs are electrically connected to their nearest neighbors to facilitate localized processing. Each PE also has 4 Kbits of RAM memory that is located off-chip due to on-chip space restrictions. The chip was fabricated through MOSIS using the 2 µm CMOS process.
Each photoreceiver consists of a p-n junction photodiode, a current mirror amplifier, and two voltage comparators. The first comparator converts the current signal to a voltage signal, while the second comparator is used to boost the voltage to 5 volts when the incident optical signal is modulated higher than 10 MHz. The photoreceiver can respond to an incident optical power of 100 µW at 14 MHz modulation.Each VCSEL driver consists of two logic inverters and a pass gate, and can operate at 20 MHz. The drive current passing through the gate and on to the VCSEL can be varied by adjusting the gate voltage, thereby affording an independent current adjustment for each VCSEL. The circuit was designed so as not to dissipate power in the OFF state.
The transparent substrate that is used is glass, as opposed to sapphire, due to cost considerations and the lack of severe thermal dissipation requirements at array sizes of only 8x8. Sapphire may need to replace glass for large size arrays. The transparent substrate is patterned with the electrical interconnects that provide connectivity between the chips and the package and between the VCSEL and CMOS chips themselves. The thickness of the substrate was selected so as to position the microlenses (lenslet array) at the correct focal length.
The lenslet array is a standard product of Nippon Sheet Glass. Its purpose is to collimate the VCSEL beams prior to their diffraction by the holographic optical interconnect element (HOIE). The center-to-center spacing of the microlenses in the array is 250 µm to match the pitch of the VCSEL array.
Theholographic optical interconnect element (HOIE) contains 64 individual phase holograms (one per VCSEL) that diffract the VCSEL beams so as to implement a non-separable perfect shuffle interconnection between two identical SPAs). The HOIE was custom designed as a four-level diffractive optical element using special CAD tools.
SPA PACKAGING
Thermosonic flip-chip bonding to mount both the VCSEL chip and the CMOS chip to the glass substrate. The principles of thermosonic flip-chip bonding are the same as those for conventional ultrasonic wire bonding except that all of the bonds must be made simultaneously. This new flip-chip technique was developed in place of the conventional techniques used in multi-chip module (MCM) fabrication because of the different environment that exists in working with optoelectronic chips.For example, solder reflow involves "dirty" processes such as solder deposition and flux during reflow, and it is very difficult to deposit solder on a chip once it has been diced. Also, the aluminum pads usually found on CMOS chips are incompatible with most solder technologies used in MCM fabrication. Conductive epoxy attachment is not feasible since the conductive particles interfere with the optical paths. Finally, thermocompression bonding involves higher temperatures and pressures, which could possibly damage the mechanical stress sensitive VCSEL chip.Thermosonic bonding uses ultrasonic energy to help "soften" the bonding material, thereby achieving bonding at lower temperature and pressure than thermo-compression bonding. For the fabrication of our smart pixel arrays, the VCSEL chips are flip-chip bonded to the base substrates by first plating gold bumps (30 µm diameter by 20 µm high) onto the gold surface contact pads of the VCSEL array. These plated contacts are then accurately positioned relative to the contacts on the substrate. The parts are then joined by a combination of heat, normal force, and ultrasonic energy.
Since the CMOS chips are received already diced, plating the bumps is not feasible. Gold balls are bonded to the aluminum contacts by a conventional wire bonding process, and the wires are subsequently removed. The remainder of the bonding process is the same as for the VCSEL chips.
The glass substrates with their bonded CMOS and VCSEL chips are then mounted in ceramic packages which have had holes drilled in their bottoms in order to provide optical access to and from the photodetectors and VCSELs, respectively, The package is then closed by adding the heat-sink/ground-plate (in contact with the back-side of the VCSEL chip through a thermally conducting grease). After closure, the lenslet arrays are glued to the exposed side of the substrate (opposite side from the bonded chips), and the hologram arrays are glued to the top of the lenslet arrays.
Figure 5
The figure is of one of SPAs as viewed through the hole in the ceramic package. The small square is the 8x8 VCSEL array, and the large rectangle is the CMOS chip (top sides of both chips visible through the glass substrate). Intra-package electrical interconnect traces on the glass are also visible. This picture was taken before the lenslet and hologram arrays were added.
OPTOELECTRONIC COMMUNICATION
Figure 6
Applications requiring the communication of digital data on the order of a trillion bits per second (terabits/second) will require the high rates achievable with optical channels. There are two applications that are driving current developments in free-space optical interconnection: telecommunication-datacommunication switching networks (e.g., ATM switches) and fine-grained parallel computers. For the former, customer access to multimedia is projected to require the switching of hundreds of thousands of subscriber lines, each running at over 500 Mb/s. This results in throughputs that are three to four orders of magnitude beyond the capacity of existing telecommunication networks, and one to two orders of magnitude beyond the projections for current electrical interconnect technology. In the case of fine-grained parallel computers, the need for tight coupling between tens of thousands of processing elements, each running near Gb/s data rates, also exceeds the projected capabilities of electrical interconnects.
An example of a fine-grained parallel system is illustrated in figure 6. This real-time graphics engine was designed to handle 1280x1024 pixels at 10 samples/pixel with 48 bits per sample for operation at 30 frames/second. Although such a performance sounds impressive, it falls more than two orders of magnitude short of rendering the number of polygons per second needed for true realism in most virtual reality applications. The desirable bandwidth would accommodate 1800x1100 pixels (HDTV) at 16 samples/pixel with 256 bits/sample for operation at 72 frames/second. This requires a board-to-board throughput of 580 Gbits/second, well in excess of the Semiconductor Industry Association (SIA) roadmap projection of a 100 Gbit/second throughput for a 256-bit wide bus by the year 2010. Many of these datacommunication switching network and parallel computer applications involve multiple boards with very high interboard throughput rates. As noted, the system above could use 580 Gbits/second. Over a bus 256 bits wide, this would require each line rate to be in excess of 2 Gbits/second. If the 128x128 SIMD array were to be replaced by a 128x128 smart pixel array (same functionality but optical I/O associated with each pixel), the line rate would have to be only 35.4 Mbits/second, a very reasonable rate.
Figure 7
The backplane of the figure 6 would be replaced by what is called a 3-D system as illustrated in figure 7 in which the board-to-board interconnects are light beams that fill much of the area vertical to the boards. The 3-D system that is assembled for FFT processing consists of just two smart pixel arrays, but the optical interconnects are bi-directional so that data are passed back and forth between the SPAs. The system's 128 PEs run at a 10 MHz clock, yielding an interconnect throughput of 160 MBytes/sec. Control of the 3-D computer is performed by a host computer through the host interface unit. Software and data are down-loaded to the interface at run time, and results are retrieved after completion.
Figure 8.
The 3-D computer is designed to operate in the Single-Instruction stream, Multiple-Data stream (SIMD) mode. Separate data are loaded into the local memory of each processor. A single instruction bus, driven by a sequencer in the host interface, simultaneously controls all the processors. Although the system is capable of general purpose processing, it was designed for FFT processing. With this in mind, the holograms were designed to implement the non-separable perfect shuffle. Details of the optics for the system are shown in figure 9. The laser beam from each VCSEL is first collimated by a microlens and then directed to a designated photodetector on the opposing SPA by a Fourier-transform type computer generated hologram and a Fourier transform lens. The system issymmetrical around the Fourier transform lens.