Research Group Name:
1. Goals:
Research on Digital System Design Methods
Emphasis on intrachip communication (NoCs)
Emphasis on fast prototyping (using FPGAs)
Emphasis on multiprocessing
Emphasis on submicron technologies
Embedded Applications Development
Emphasis on telecommunication systems
Emphasis on biotechnology systems
2. Research lines and interests:
Intrachip Communication (NoCs)
Multiprocessor Systems on a Chip (MPSoCs)
Fast Prototyping of Digital Systems
Non-synchronous Circuit and System Design
Embedded Systems Design
Telecommunication Applications
Biotechnology Applications
3. Industrial and Academic Partners and Joint Initiatives:
DATACOM Telemática – Poa-RS
PARKS S/A – Poa-RS
LIRMM (U. Montpellier) - France
U. Darmstadt - Germany
U. York - United Kingdom
Microelectronics Group – UFRGS – Poa-RS
4. Members (Faculty):
César Marcon (also in GSE)
Eduardo Bezerra (also in GSE)
Fabiano Hessel (also in GSE)
Fernando Moraes
Ney Calazans (head)
5. Graduate Students: past and present (only members)
· Fernando Moraes – Advised 13 MSc Dissertations, 3 MSc (co-adv. at UFRGS), 3 PhD (co-adv. at UFRGS). Currently advising 3 MSc (2 new entering) and 4 PhD Students.
· Ney Calazans - Advised 13 MSc Dissertations, 1 PhD (co-adv. at UFRGS). Currently advising 4 MSc (2 new entering) and 3 PhD Students (1 new entering).
*For other GAPH members, see description of GSE group
6. Funded Research Projects
· X10Giga – FINEP/DATACOM - 10 Gbps optical fiber equipment
o PUCRS, Datacom, UFCe, Instituto Atlântico
· TETHA – FINEP/DATACOM – Fast/Gbit Ethernet NoC Switch
o PUCRS, Datacom
· Brazil-IP – 1st phase - Human resources for IP design
o PUCRS, UFMG, UFPe, UFPb, UFRGS, UnB, UniCamp, USP
· Utilização de Redes Intra-Chip em SoCs: Projeto, Reconfiguração e Teste – International Cooperation
o PUCRS, LIRMM (France), UFRGS
· Infra-Estrutura para Projeto de MPSoCs (CNPQ UNIVERSAL 2007 - 471134/2007-4 – Moraes e Marcon e CNPq PQ 300774/2006-0 - Moraes)
· ACÁCIA – Arquiteturas e Circuitos Assíncronos: Comunicação, Infra-estrutura e Aplicações (CNPq PQ 2009 - Ney)
7. Major results (papers, patents, software, etc.)
· HERMES: an Infrastructure for Low Area Overhead Packet-switching Networks on Chip. Integration The VLSI Journal, 2004. Cited 131 times in Google Scholar.
· Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses. IEEE Transactions on Education, 2001. Cited 23 times in Google Scholar.
· Design and prototyping of an E1 Drop_Insert soft core. IEE Proceedings. Communications, 2003. Cited 12 times in Scopus.
· Comparison of NoC Mapping Algorithms Targeting Low Energy Consumption. IET Computers and Digital Techniques, 2008.
· Evaluation on FPGA of Triple Rail Logic Robustness Against DPA and DEMA. In: DATE´09, 2009.
· MultiNoC: A Multiprocessing System Enabled by a Network on Chip. In: DATE´05, 2005. (Best Conceptual Design Prize by EuroASIC)