G. PULLA REDDY ENGINEERING COLLEGE (Autonomous): KURNOOL

Accredited by NBA of AICTE and NAAC of UGC

An ISO 9001:2008 Certified Institution

Affiliated to JNTUA,Anantapur

M.Tech Syllabus- Scheme 2013

(VLSI and Embedded Systems)

TWO YEAR M.TECHDEGREE COURSE(SCHEME-2013)

Scheme of instruction and Examination

(Effective from 2013-2014)

M.Tech - I Semester VLSI and Embedded Systems Scheme:2013

S. No / Course No. / Course Title / Credits / Scheme of Instruction periods/week / Scheme of Examination
Maximum Marks
L / T / P / End Exam / Internal Assessment / Total
1. / EC851 / Advanced Problem Solving(APS) / 3 / 3 / - / – / 70 / 30 / 100
2. / EC852 / CMOS VLSI Design(CMOS) / 3 / 3 / – / 70 / 30 / 100
3. / EC853 / Modeling of Advanced Digital System design using HDL (MAD-HDL) / 3 / 3 / - / – / 70 / 30 / 100
4. / EC854 / Advanced Embedded Systems –I(AES-1) / 3 / 3 / – / 70 / 30 / 100
5 / Elective - I / 3 / 3 / – / 70 / 30 / 100
6. / EC855 / Advanced VLSI and Embedded Systems Lab (AVESP) / 2 / – / 3 / 50 / 50 / 100
7. / EC856 / Seminar / 1 / - / - / - / - / 100 / 100
Total / 18 / 15 / - / 3 / 400 / 300 / 700

1

Scheme : 2013

L / T/D / P / C
3 / 0 / 0 / 3

Internal Assessment: 30

End Exam : 70

End Exam Duration: 3 Hrs

Course Objectives:

  1. To make students familiar with graphs and their properties in advanced level.
  2. To make students familiar with spanning tree and Shortest path algorithms.
  3. To make students familiar with critical path concepts used in VLSI Signal Processing.

Course outcomes:

  1. Students will be able to know the concepts of DFG used in VLSI Signal Processing.
  2. Students will be able to solve problems arise in complex graphs like travelling Salesman, Mohammad’s scimitar, Star of David etc…

Introduction: Basic definitions, Results and examples relating to Graph theory, Self–complementing graphs and properties of graphs, Trees, Spanning tree & directed graphs.

Classification of Graphs: Definitions of strongly, Weakly, Unilaterally connected graphs and deadlocks, Metric representation of graphs. Classes of graphs, Standard results relating to characterization of Hamiltonian graphs, Standard theorems

Self–Centered graphs and related theorems: Chromatic number vertex and edge , Application to coloring, Linear graphs, Euler’s formula.

Graph algorithms: DFS, BFS algorithms, Minimum spanning tree and maximum spanning tree algorithm. Directed graphs algorithms for matching, Properties flow in graph and algorithms for max flow. PERT-CPM, Complexity of algorithms, P–NP, NPC, NP hard problems and examples.

Linear integer and dynamic programming: Conversions of TSP, Maximum flow, Shortest path problems. Branch bound methods, Critical path and linear programming conversion. Flow shop scheduling problem, Personal assignment problem, Dynamic programming - TSP, Best investment problems.

Reference Books:

1. C. Papadimitriou & K. Steiglitz, Combinational Optimization, Prentice Hall, 1982.

2. H. Gerej, Algorithms for VLSI Design Automation, John Wiley, 1992.

Reference Books:

3. B. Korte & J. Vygen, Combinational Optimization, Springer Verilog, 2000.

4. G.L. Nemhauser & AL Wolsey, Integer & Combinatorial Optimization, John Wiley, 1999.

5. W.J. Cook et al, Combinational optimization, John Wiley,2000.

Note : The question paper shall consist of Eight questions out of which the student shall

answer any Five questions

Scheme : 2013

L / T/D / P / C
3 / 0 / 0 / 3

Internal Assessment: 30

End Exam : 70

End Exam Duratio : 3 Hrs

Course Objectives:

1. To make students aware of Semi conductor Device Physics.

2.To make students understand various inverter topologies in

PMOS, NMOS, CMOS, BICMOS.

3. To make students understand fabrication of IC in different technologies.

Course Outcomes:

1.Students will be able to grasp semi conductor physics.

2.Students will be able to know VLSI processing technology.

3.Students will be able to construct various circuits ,Stick diagrams,Layouts

using CMOS.

Device Physics: Review of MOS Transistor Theory, MOS Device Equations I/V Basic DC Equations, Concept of Threshold voltage, Second Order Effects, Small Signal ac Characteristics.
Inverter Analysis: Complementary CMOS Inverter DC Characteristics, βn/βp Ratio, Noise Margin, CMOS Inverter as an Amplifier, Static Load CMOS Inverters I/V Pseudo NMOS Inverter, Saturated Load Inverters, Cascode Inverter, TTL Interface Inverter, Differential Inverter, Transmission Gate, Tri-state Inverter, BiCMOS Inverters.
Fabrication Process: Basic MOS Technology, NMOS and CMOS Process Flow, Stick Diagrams Design Rules, Layout Design and Tools, Latch-up in CMOS.
Circuit Characterization and Performance Estimation: Resistances and Capacitances Estimation, SPICE Modeling, Switching Characteristics, Delay Models, Rise and Fall times, Propagation Delays, Body Effect. CMOS Gate Transistor Sizing, Power Dissipation, Design Margining, Scaling Principles.
CMOS Circuit and Logic Design: CMOS Logic Gate Design, Basic Physical Design of Simple Logic Gates, CMOS Logic Structures, Clocking Strategies, Low Power CMOS Logic Structures, Chip Input and Output (I/O) Structures.
VLSI Design Methodologies: VLSI Design Flow, Structured Design Strategies, VLSI Design Styles, Chip Design Options.
Subsystem Structures: Arithmetic Logic Unit (ALU), Shifters, Memory Elements, High Density Memory Structures, Finite State Machines (FSM) and Programmable Logic Arrays (PLA).

Text Books:

1. Weste Kamran Eshraghian, Principles of CMOS VLSI design , a Systems Perspective by NEILHE,

Pearson Education Series, Asia, 2002.

2. Wolf, Modern VLSI Design, Pearson Education Series, 2002.

Reference Books:

3. Jean M. Rabey, Digital Integrated Circuits, Prentice Hall India, 2003

4. M. Shoji, CMOS Digital Circuit Technology, Prentice Hall, 1987.

Note : The question paper shall consist of Eight questions out of which the student shall

answer any Five questions

Scheme : 2013

L / T/D / P / C
3 / 0 / 0 / 3

Internal Assessment: 30

End Exam : 70

End Exam Duration: 3 Hrs

Course Objectives:

  1. To make familiar with architecture of PLD’s & industry standard FPGA
  2. To give understanding of various placement and routing algorithms.
  3. To give understanding of HDLs(Hardware Description Languages) like VHDL & Verilog

Course Outcomes:

1. Students will be able to design systems with standard FPGAs

2. students will be able to know various styles of modeling like

Dataflow,Behavioural,Structural modeling.

3. Students will be able to design (coding)digital systems in both VHDL&Verilog.

Introduction to PLDs & FPGAs: ROMs, Logic array (PLA), Programmable array logic, GAL, bipolar PLA, NMOS PLA, PAL 14L4, Xilinx logic cell array (LCA) – I/ O Block, Programmable interconnect, Xilinx , 3000 series and 4000 series FPGAs. Altera CPLDs, Altera FLEX 10K series PLDs.

Placement and routing: Mincut based placement, Iterative improvement placement, Routing, Segmented channel routing , Maze routing , Routability and routing resources , Net delays.

Introduction to VHDL : Digital system design process, Hardware simulation, Levels of abstraction, VHDL requirements, Elements of VHDL, Top down design VHDL operators, Timing, Concurrency, Objects and classes, Signal assignments, Concurrent and sequential assignments.

Structural, Data flow & Behavioral description of hardware in VHDL : Parts library, Wiring of primitives, Wiring of iterative networks, Modeling a test bench, Top down wiring components, Subprograms. Multiplexing and data selection, State machine descriptions, Open collector gates, Three state bussing, Process statement, Assertion statement, Sequential wait statements, Formatted ASCII I/O operations MSI based design.

Introduction to Verilog HDL : Lexical conventions, Data types, System tasks and Compiler Directives−Modules and Ports−Gate Level Modeling with Examples, Design options of Digital Systems, Hierarchical system design, ASIC designs, PLD modeling, CPLD and FPGA devices, Synthesis, Design flow of ASICs and FPGA based system, design environment and constraints logic synthesizers, Language structure synthesis, Coding guidelines for clocks and reset.

Text Books:

1. P.K. Chan & S. Mourad, Digital Design sing Field Programmable Gate Array, 1st Edition,

Prentice Hall, 1994.

2. J. V. Old Field & R.C. Dorf, Field Programmable Gate Array, John Wiley, 1995.

3. M. Bolton, Digital System Design with Programmable Logic, Addison Wesley, 1990.

Reference Books:

4. Thomas E. Dillinger, VLSI Engineering, Prentice Hall, 1st Edition, 1998.

5. Douglas Perry, VHDL, 3rd Edition, McGraw Hill 2001.

6. J. Bhasker, VHDL, 3rd Edition, Addison Wesley, 1999.

7. Ming-Bo Lin., Digital System Designs and Practices Using Verilog HDL and FPGAs, Wiley,

2008.

8. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Pearson Education, 2005.

Note : The question paper shall consist of Eight questions out of which the student shall

answer any Five questions

Scheme : 2013

L / T/D / P / C
3 / 0 / 0 / 3

Internal Assessment: 30

End Exam : 70

End Exam Duration: 3 Hrs

Course objectives:

  1. To make students familiar with basic embedded systems and SOCs
  2. To make students familiar with processor organizations and memory overview.
  3. To make students understand Microcontrollers, RISC machines and ARM processors.
  4. To make students write programs in ALP.

Course Outcomes:

  1. Students will be able to understand embedded systems and SOCs
  2. Students will be able to write various programs in Assembly Language Programm
  3. Students will be able to use ARM processors in their projects and industry.

Introduction to embedded systems: Background and History of Embedded Systems, Definition and Classification, Programming languages for embedded systems, Desirable characteristics of programming languages for embedded systems, Low-level versus high-level languages, Main language implementation issues, Control, typing, Major programming languages for embedded systems, Embedded System on a Chip (SoC) and

the use of VLSI designed Circuits.

Processor and Memory Organization: Structural units in processor, Processor selection for an embedded system, Memory devices, Memory selection, Allocation for memory to program segments and blocks and memory map of a system, DMA, Interfacing processor, I/O Devices - Device I/O Types and Examples I/V Synchronous – ISO synchronous and Asynchronous Communications from Serial Devices, Examples of Internal Serial–Communication Devices – UART and HDLC, Parallel Port Devices, Sophisticated interfacing features in Devices/Ports- Timer and Counting Device
Microcontroller: Introduction to Microcontrollers, Microprocessors Vs Microcontrollers, PSoC and MCS – 5x Family Overview, Important Features, Architecture, Pin Functions, Architecture,

Addressing Modes, Instruction Set, Instruction Types.

ARM Processor as System-on-Chip: Acorn RISC Machine, Architecture inheritance, ARM programming model, ARM development tools, 3 and 5 stage pipeline, ARM organization, ARM instruction execution and implementation, ARM Coprocessor Interface.

ARM Assembly Language Programming: ARM instruction types, Data transfer, Data processing and control flow instructions, ARM instruction set, Coprocessor instructions. Architectural Support for High Level Language: Data types, Abstraction in Software design, Expressions, Loops, Functions and Procedures, Conditional Statements, Use of Memory.

Text Books:

1. Steve Furber, ARM System on Chip Architecture, 2nd Edition, Addison WesleyProfessional, 2000.

2. Ricardo Reis, Design of System on a Chip: Devices and Components, 1st Edition, Springer, 2004.

3. Raj Kamal, Embedded Systems Architecture, Programming and Design, 2nd Edition, TMH, 2006.

4. Jonathan W Valvano, Embedded Micro Computer Systems, Real Time Interfacing,1st Edition,

Books / Cole,Thomson learning 2006.

Reference Books:

5. Arnold S Burger, Embedded System Design An Introduction to Processes, Tools and Techniques,

1st Edition, CMP Books, 2007.

6. David.E. Simon, An Embedded Software Primer,2nd Edition, Pearson Edition, 2009.

7. Andrew N.sloss, Dominic Symes, Chris Wright, ARM System Developer’s guide,1st Edition, Elsevier

Publications 2005.

Note : The question paper shall consist of Eight questions out of which the student shall

answer any Five questions

Scheme : 2013

L / T/D / P / C
3 / 0 / 0 / 3

Internal Assessment: 50

External: 50

Exam Duration: 3 Hrs

  1. Digital Circuits Description using Verilog and VHDL
  1. Verification of the Functionality of Designed circuits using function Simulator.
  1. Timing simulation for critical path time calculation.
  1. Synthesis of Digital circuits
  1. Place and Route techniques for major FPGA vendors such as Xilinx, Altera and Actel etc.
  1. Implementation of Designed Digital Circuits using FPGA and CPLD devices.
  1. Microcontroller programming using PSoC and MC- 5x series

a)Toggling the LEDs,

b)serial data transmission,

c)LCD and Key pad interface

1

TWO YEAR M.TECH. DEGREE COURSE

Scheme of instruction and Examination

(Effective from 2013-2014)

M.Tech - II Semester VLSI and Embedded Systems Scheme: 2013

S. No / Course No. / Course Title / Credits / Scheme of Instruction periods/week / Scheme of Examination
Maximum Marks
L / T / P / End Exam / Internal Assessment / Total
1 / EC857 / Algorithms for VLSI(AFV) / 3 / 3 / - / – / 70 / 30 / 100
2 / EC858 / Analog VLSI Design(AVLSI) / 3 / 3 / - / – / 70 / 30 / 100
3. / EC859 / Low Power VLSI Design(LVD) / 3 / 3 / - / – / 70 / 30 / 100
4 / EC860 / Advanced Embedded Systems – II(AES-II) / 3 / 3 / - / – / 70 / 30 / 100
5. / Elective - II / 3 / 3 / - / - / 70 / 30 / 100
6. /

EC861

/

Advanced EDA Lab(EDAP)

/ 2 / – / - / 3 / 50 / 50 / 100
7. / EC862 / Seminar / 1 / - / - / - / - / 100 / 100
Total / 18 / 15 / - / 3 / 400 / 300 / 700

1

Scheme : 2013

L / T/D / P / C
3 / 0 / 0 / 3

Internal Assessment: 30

End Exam : 70

End Exam Duration : 3 Hrs

Course Objectives:

  1. To make students familiar with various algorithms like partitioning, Floor planning, P&R in VLSI.
  2. To make students familiar with logic simulation and verification.
  3. To make students familiar with Synthesis algorithms.
  4. To make students familiar with multi chip modules

Course Outcomes:

  1. Students will be able to understand various algorithms commonly used in VLSI.
  2. Students will be able to understand optimization for synthesis.
  3. Students will be able to understand latest trends in physical design like MCMs.

Basic Algorithms and Data structures : Data Structures and Basic Algorithms , Algorithmic Graph Theory and Computational complexity, Tractable and Intractable problems, General Purpose Methods for Combinational Optimization.

Partitioning, Floor planning, Placement & Routing Algorithms : Partitioning, Problem formulation, Classification of partitioning algorithms, Group migration algorithms, Simulated annealing and evolution, Performance driven partitioning, Floor planning and pin assignment, Problem formulation, Classification of floor planning algorithms, Classification of pin assignment algorithms, Placement, Problem formulation, Classification of placement algorithms, Simulation based placement, Partitioning based placement, Performance driven placement, Routing, Global routing, Problem formulation, Classification of global routing algorithms, Detailed routing, Problem formulation, Classification of detailed routing algorithms.

Simulation, Logic synthesis & Verification : Simulation, Different levels of simulation, Logic synthesis & Verification, Basic issues in combinational logic synthesis, Binary decision diagrams, ROBDD principles, Implementation and construction, Manipulation, Variable ordering, Applications to verification and combinatorial optimization.

High level synthesis & Compaction : Hardware models for high level synthesis, Internal representation of the input algorithm, Allocation, Assignment and scheduling, Compaction, Problem formulation, Classification of compaction algorithms, One dimensional compaction, One and a half dimensional compaction, Two dimensional compaction, Hierarchical compaction, Recent trends in compaction.

Physical Design Automation of FPGAs & MCMS : Physical Design Automation of FPGAs, FPGA technologies, Physical design cycle for FPGAs, Partitioning, Routing, Physical design automation of MCMS, MCM technologies, MCM Physical design cycle, Partitioning, Placement, Routing , VHDL, Verilog, Implementation of simple circuits using VHDL and Verilog.

Text Books:

1. N.A.Sherwani, Algorithms for VLSI Physical Design Automation, 3rd Edition, Kluwer

Academic, 1999.

2. S.H.Gerez, Algorithms for VLSI Design Automation, John Wiley, 1998.

Note : The question paper shall consist of Eight questions out of which the student shall

answer any Five questions

Scheme : 2013

L / T/D / P / C
3 / 0 / 0 / 3

Internal Assessment: 30

End Exam : 70

End Exam Duration : 3 Hrs

Course objectives:

  1. To make students familiar with advanced current mirrors and their behavior at high frequency and low frequencies.
  2. To make students familiar with design of OP-AMPs, comparators in BiCMOS.
  3. To make students familiar with S&H, ADC,DAC etc..
  4. To give in detail view of filters used in sampling, Analog Multipliers.

Course Outcomes:

  1. Students will be able to design current mirrors and high impedence current mirrors.
  2. Students will be able to design Differential OP-AMP,S&H Circuits
  3. Students will be able to design analog multipliers and able to analyze their operation.

Basic current mirrors and single stage amplifiers: Simple CMOS current mirror, common source, Common gate amplifier with current mirror active load, Source flower with current mirror to supply bias current, High output impedance current mirrors and bipolar gain stages, Frequency response.

Operational amplifier design and compensation: Two stage CMOS operational amplifier, feedback and operational amplifier compensation, advanced current mirrors, Folded-cascode operational amplifier, Current mirror operational amplifier, Fully differential operational amplifier, common mode feedback circuits, Current feedback operational amplifier. Comparator, Charge injection error, Latched comparators, BiCMOS comparators.

Sample and hold and switched capacitor circuits: MOS, CMOS and BiMOS sample and hold circuits, Switched capacitor circuits, Basic operation and analysis first order and biquad filters, Charge injection, Switched capacitor gain circuit, Correlated double sampling techniques, Other switched capacitor circuits.

Data converters: Ideal D/A and A/ D converters, Quantization noise, Performance limitations. Nyquist rate D/A converters, Decoder based converters, Binary scaled converters, Hybrid Converters, Nyquist rate A/ D converters, Integrating, Successive approximation, Cyclic flash type, Two step interpolating, Folding and pipelined, A/D converters.

Over sampling converters and filters: Over sampling with and without noise haping, Digital decimation filter, High order modulators, Band pass over sampling converters, Practical Considerations, Continuous time filters, Mixers, PLLs, Multipliers.

Text Books:

1. Paul.R. Gray & Robert G. Major, Analysis and Design of Analog Integrated Circuits, John Wiley

& sons, 2004.

2. David Johns, Ken Martin, Analog Integrated Circuit Design, John Wiley & sons. 2004.

Reference Books:

3. Behzad Razavi, Design of Analog CMOS Integrated Circuits, Tata Mc Grah Hill. 2002.

4. Jacob Baker.R.et.al., CMOS Circuit Design, IEEE Press, Prentice Hall, India, 2000.

5. Mohamed Ismail, Analog VLSI , Mc Graw hill, 1st Edition, 1994.

Note : The question paper shall consist of Eight questions out of which the student shall

answer any Five questions

Scheme : 2013

L / T/D / P / C
3 / 0 / 0 / 3

Internal Assessment: 30

End Exam : 70

End Exam Duration : 3 Hrs

Course Objectives:

  1. Students will be able to understand various types of power dissipation in CMOS.
  2. Students will be able to estimate power.
  3. Students will be able to reduce the power for the given circuits in CMOS.

Course Outcomes:

  1. Students will be able to estimate different powers in CMOS
  2. Student will be able to minimize static, dynamic power dissipation.
  3. Students will be able to minimize power for software design like ARM,XILINX etc..

Introduction and need of low power design: Sources of power dissipation, MOS transistor leakage components, SOI technology, Fin FET, Back gate FET, Power and energy basics, Power dissipation in CMOS circuits, Energy–delay product as a metric, Design strategies for low power.