P.S: All the Same PIN Name on the Schematic Are Connected Together

Detailed Design

(1) Power Supply

Figure 1: Schematic of the power supply.

We decided to power up the whole circuit using +15V and -15V. This is chosen because the amplifiers need that much power to turn it on. On the schematic above, we can see that we also use some voltage regulators. These voltage regulators are used to reduce the initial voltages. The reason we do that is because some circuits only need 5V supply instead of 15V supply. The connection on the voltage regulator can be seen on the datasheet. These supply voltages to the circuit are connected by the banana jack. Van means the analog voltage supply and Vd means the digital voltage supply. Moreover, we only made one ground for the whole circuit called AGND (Analog Ground). This is because the digital component will no be used that often, so the effect of the DGND (Digital Ground) will be insignificant.

P.S: All the same PIN name on the schematic are connected together.

(2) Two-Stage Op-amp

Figure 2: schematic of the two-stage op-amp

The two-stage op-amp is designed based on the paper written by Dr. Geiger on amplifiers with maximum bandwidth. The two-stage op-amp should be able to produce different gains setting at the certain frequency (refer to the limitation table on the Final Document). The explanation on the schematic above as follow:

· The two op-amp that we used are AD8007. Those are current feedback amplifiers. If these op-amps don’t meet the design requirement, then replace these op-amps with AD8021. AD8021 is a voltage feedback amplifier. The reason we picked two different op-amps was because Dr. Geiger was not sure if the topology would work with the current feedback or voltage feedback amplifiers. This will be a good idea to try them both. Team should read on the datasheet on how to connect the compensated capacitors around the op-amp.

· All the input and output signal are coming from the BNC connectors (BNC1 and BNC2). Each BNC connector is then connected to 49.9Ω resistor. This resistor is connected in parallel and in series to the BNC. The series 49.9Ω resistors are always on the driver side of the transmission line (look at BNC 2 at vout line). The parallel 49.9Ω to ground is always on the load end of the transmission line (look at BNC 1 at the IN). Every BCN connector in the design should be connected to the 49.9Ω.

· All the switches used in the two-stage op-amp are the DIP-switches (SW100-W124). This DIP-switch is used so we can change the gains setting easily and manually.

· The reason we put SW124 is because when the design is used to test different gains setting, we don’t need to connect it to the comparator (AD790). The only time the op-amp is connected to the comparator is when we want to test the DC-Offset.

· The low pass filter R117 and C108 is connected to the output is because every time the output voltage goes from positive to negative the comparator output will transition from a logic 1 to a logic 0. Noise would cause the comparator to transition many times when we are close to ground and that we would not be able to tell exactly when it was really at ground. So we might want to try to filter out some of the noise. The R117 is placed at 10Ω, so it won’t be any offset problem produced by the comparator and it is also to make sure the comparator could handle the current that coming in.

(3) DC-Offset

Figure 3: Schematic of the DC-Offset

The schematic of dc-offset design was initially done by the previous team (phase III). Several changes to the DC-offset:

· We made changes to the resistor values so that the (voffset) could have enough voltage to be canceled. The analysis can be seen on the final report.

· We also added a buffer at the output of the DAC (AD5541). This is because the DAC is capable to drive a minimum 60KΩ load. We only use 4.02KΩ load on the circuit. This buffer will provide higher impedance to the circuit.

· The real voltage reference 2.5V is used on the circuit as well (VR3). This voltage reference just acts like a zener. The exact 2.5V for the reference of the DAC will improve the performance of the DAC.

· When testing the DC-offset, connect the output of the amplifier to the comparator. This comparator is used to comparator the output voltages to 0V.

(4) FPGA

The FPGA circuit is basically done from the first place. We only have to find the right FPGA from the digikey. The FPGA is used to provide the right input voltage for the DAC in order to correct the offset problem. We didn’t make any changes to the FPGA circuit. All the code was also done by previous team (phase III).

(5) Board

The board should have the same pins name as the schematic. All the components can be placed easily based on the name shown in the schematic.

Important things:

· Be careful for C401 capacitor, which is connected to the -15V power supply. The polarization was wrong on the board. Unfortunately, we figured it out after the board was made. Look at the final board on the website. We have updated the right one.

· If you look at the PCB design and click on one of the pins for U1 or U2 you will see that the pins are connected wrong. Pin 6 is the output of the op-amp, but it is actually connected to the net for pin2 (the part is rotated 180 degrees). Confirm this problem with Teradyne if they’ve fixed the problem on the board.

· Pins 1 and 3 of VR1 are reversed.

Pins 2 and 3 of VR2 are reversed.

Pins 1 and 3 of VR4 are reversed.

Again confirm this problem with Teradyne if they’ve fixed it on the board.

(6) Component

Unfortunately team bought the dip switches, socket for FPGA, and the FPGA (SW100-Sw300, #123 and U7 in the BOM) wrong. So please look at the BOM that we have updated. Buy those components and solder them on the board before it can be tested.