Observations in Characterizing a Commercial MNOS EEPROM for Space

E. E. King, R. C. Lacoe, G. Eng, and M.S. Leung

The Aerospace Corporation

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El Segundo, CA

(310) 336-7898,

Abstract

This paper describes our efforts to characterize a commercial 1-Mbit EEPROM (the Hitachi HN58C1001) with the objective of ensuring that it is capable of retaining stored data for long periods of time (10-20 years) while dormant in a space environment. The HN58C1001 is a CMOS part that incorporates a Metal Nitride Oxide Semiconductor (MNOS) field effect transistor (FET) for data storage [1,2,3]. A data bit is stored in the MNOS transistor in the form of charge trapped in the thin silicon nitride film that is formed over the transistor’s channel. The presence or absence of this trapped charge dictates the transistor’s threshold voltage. The transistor is interrogated by applying a voltage between the drain and source with a reference voltage applied to the gate. A readout amplifier senses the drain current to determine whether the transistor has been programmed to be in the ‘1’ or ‘0’ state.

The lifetime tests show that the activation energy for data retention is probably not a single value, but is consistent with the 1 eV value published by Hitachi [1]. This result combined with the push out of the read out access time measured during the aging tests indicate that the data retention lifetime for this part is well over 20 years as long as the temperature remains at or below 70C. In addition, total ionizing dose (TID) irradiation tests showed that the part is not affected by exposure to total dose up to 78 krad(Si) (unbiased irradiation) and subsequent aging tests on the irradiated parts showed that TID exposure up to this level has little, if any, effect on the data retention lifetime.

Our characterization tests also revealed a number of interesting electrical behaviors for the part, however, that should be considered in its application and qualification. First, it was found that the part could easily be triggered into an internal data rewrite condition on power-up or power-down if considerable care was not taken to prevent it. Lockout of this condition was accomplished in our tests by using a pull-down resistor on the RESET pin to ensure that it was always held at chip ground except when it was intentionally driven high. However, Hitachi also describes a software data protection method to prevent unintentional programming in their specification, which if used in conjunction with strict control of the RESET pin, should provide a high degree of protection against an unintentional rewrite.

When the data-out lines are first enabled, they begin to go high. If a ‘0’ has been written into the memory element that is being read out, one must wait for the output corresponding to this data bit to be driven to a ‘0’ by the sense/readout amplifier. As a result, it is rare for a failure to be observed when the expected output is a ‘1.’ On the other hand, if the charge on a memory transistor that has been programmed to be a ‘0’ has been reduced during aging (or the readout sense amplifier is degraded), the time it takes for the output bit to be driven to the ‘0’ state can increase, resulting in an error if the data are read out too soon. As a result, design margin can generally be improved by extending the readout access time. However, occasional instances were observed during the aging tests in which a data output signal oscillated for some considerable period of time during which the data bit was supposed to be valid. This behavior is illustrated in Figure 1. The oscillatory behavior was transitory and generally could not be repeated after a few hours had elapsed. Since we did not have enough information about the design of the part to model this intermittent behavior, it was not possible for us to conclude that extending the readout time was an effective way to ensure reliable part operation.

Finally, a test pattern was developed to optimize screening parts out of the population that might be prone to early failure. Based on the test experience described above, the pattern consisted of a high percentage of ‘0’s. A sub-pattern was written periodically throughout the memory address space to detect a pattern sensitivity that was found on aged parts in which failures were observed when reading out a word containing a large number of ‘0’s that was preceded by a word containing a large number of ‘1’s. The test pattern also contained a number of words that could only be read out correctly if every address bit was capable of toggling.

(a) (b)

Figure 1. Scope traces illustrating the intermittent readout failure. The x-axis is 200ns per major division. For the first data readout period shown in (a), I/O1 and I/O2 are ‘1’ and ‘0,’ as programmed. The same outputs are shown in (b) for a slightly decreased, but still within specification, power supply voltage. These oscillations on the I/O lines are likely to result in data error even if the access times are significantly extended.

References:

  1. Kamigaki, Yoshiaki, et al., “Yield and Reliability of MNOS EEPROM Products,” IEEE J. of Sol.-State Circuits, Vol. 24, No. 6, December 1989, p. 1714
  1. McWhorter, P. J., S. L. Miller, and T. A. Dellin, “Modeling the memory retention characteristics of silicon-nitride-oxide-silicon nonvolatile transistors in a varying thermal environment,” JAP, 68 (4), 15 August 1990, p. 1902
  1. Wu, Ken, et al., “A Model for EPROM Intrinsic Charge Loss through Oxide-Nitride-Oxide (ONO) Interpoly Dielectric,” IEEE Proc. of the IRPS, 1990, p. 145

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