EO212 1 / 11
SCHOOL OF ENGINEERING
MODULAR HONOURS DEGREE COURSE
LEVEL 2
SEMESTER 2
2004/2005
ANALOGUE ELECTRONICS
Examiners: Dr C Garrett/ Dr SS Singh
Attempt FOUR questions only Time allowed: 2 hours
Total number of questions = 6
All questions carry equal marks.
The figures in brackets indicate the relative weightings
of parts of a questions.
Special requirements: None
1)This question consists of 10 parts. Each part is worth 2.5 marks giving 25 marks in total
a)Sketch a graph of VBE against IC for an NPN bipolar transistor. On this graph mark the point identifying classesA and B amplifier operation.
b)Draw the symbol of a PNP bipolar transistor, label the terminals, and indicate the normal direction of terminal voltages.
c)An NPN bipolar transistor is used in an emitter-follower configuration. The dc base voltage is 5 V and collector voltage is 10 V. If the transistor is operating normally what dc voltage would you expect to see at the emitter?
d)A mathematical model of a MOSFET in it’s constant current region is:
Assuming the gate is held at 3 V, the source is 0V and the drain is connected to 10 V via a series resistor of 20 Ohms. Determine the drain voltage.
e)Sketch the transfer characteristics of three N-channel FET’s on the same ID/VGS graph. The three devices are: i) JFET, ii) Depletion-mode MOSFET, iii) Enhancement-mode MOSFET. Label each graph to indicate each device.
f)State the equation that relates the voltage and current gradient of an inductor. With reference to this relationship explain how the current in the inductor may be zero at the time that the voltage is non zero.
g)Write down the equation that relates the current and voltage gradient of a capacitor. With reference to this relationship explain how the voltage across the capacitor may be zero at the time that the current is non zero.
h)Explain why the current into the input of an operational amplifier which has negative feedback, can be assumed to be zero.
i)With reference to Ohms law, explain why a resistance which has a positive temperature coefficient will result in a voltage rise with rising temperature even though the current it supports is constant.
j)With reference to Ohms law, explain why a practical voltmeter inserted across any component in a circuit cannot measure the true voltage. (25)
2)
a) Sketch the full hybrid-pi model of an NPN bipolar transistor labelling all nodes, and
components. There is no requirement to include voltages and currents on your sketch. (6)
b) Sketch a simplified hybrid-pi model suitable for low-frequency approximate analysis. Label the component parameters. (4)
c)Figure Q2 shows a single transistor amplifier. The transistor hFE is known to be approximately 300. Calculate the small-signal voltage gain and hence the approximate rms voltage across the load RL. Assume the input voltage
V = 2 + 0.04sin(t) volts and that the frequency is high enough to make the capacitor reactance’s negligible. Show all working and include in your answer an ac equivalent circuit. (10)
Figure Q2 Single Transistor Amplifier
d) Now assume that the voltage gain frequency -3 dB point of the amplifier in figure Q2. is dominated by the emitter decoupling capacitor (CE). If CE in parallel with 1.5 k = Z, then develop an equation for the small-signal voltage gain in terms of
Z and hFE.(5)
3)The circuit in FigureQ3, is a simple switched inductive load. The switch is initially open. At the time t=0 the switch is operated, allowing current and magnetic field to build up in the inductor. After a time interval t1 the switch is operated a second time to ‘break’ the current loop in the circuit.
a)Describe what happens to the current and the magnetic energy in the circuit from the instant the switch is operated at time t=0. Ensure that your explanation includes justification with reference to the equations V=Ldi/dt and E=0.5Li2 as well as voltage and current flow directions. (8)
b) Illustrate your explanation by sketching a graph of inductor current against time ‘t’ from the instant that t=0 to the instant that t=t1 . Include on your graph a clear indication of the times at which the switch is operated. Indicate the value of any significant gradients on the graph. (5)
c) Describe what happens to the current in the circuit from the time t1 when the switch
is operated a second time to ‘break’ the current loop in the circuit. You may assume that the switch has a small but significant stray capacitance ‘C’. Ensure that your explanation is justified by including reference to the equation E=0.5Li2. Reference
to the use of additional equations must be made clear.(7)
d)Illustrate your explanation by sketching a graph of inductor current against time ‘t’ from the instant that t=t1 to sometime after, when the current has a value lower than that value at time t=t1. Include on your graph a clear indication of the times at which the switch is operated. Explain why the graph of inductor current is the shape you
have drawn. Refer to appropriate portions of the graph to support your explanation. (5)
QUESTION 3 CONTINUES ON PAGE 5/11
4)The circuit in figure Q4 shows a simple NPN transistor circuit, in which the transistor is forward biased. The transistor has a minimum current gain hFE of 200. The supply voltage to the circuit is -12.0V and the transistor base and collector resistors are 10k and 1k respectively. Take account of the polarity of both the voltages and currents with respect to the voltage and current arrow directions at all times.
a)Calculate for the circuit the size of the input voltage that will guarantee to bias the transistor into saturation. Take into account the finite base-emitter voltage drop of 0.6V as well as the finite collector-emitter voltage drop of 0.4V when the transistor is saturated. Show all mathematical steps in your derivation. (8)
b)Evaluate the input voltage to the circuit that will cause the output voltage to be -6.0V at minimum hFE. Take into account the finite base-emitter voltage drop of 0.6V and show all mathematical steps in you calculations. (7)
c)Sketch a graph of input voltage verses output voltage for the circuit, indicating at which input voltage value, transistor saturation occurs. Indicate on the graph the input voltage at which the transistor begins to turn on. Ensure that the sign of both voltages are represented correctly on the graph. (4)
d)If a resistive load of value 2.0k is connected across the circuit output voltage, by how much must the circuit input voltage be changed by in order that the output voltage remains at -6.0V. (6)
QUESTION 4 CONTINUED ON PAGE 7/11
NPN Transistor Circuit
Figure Q4
5)Operational amplifiers are known to have certain limitations that an ideal operational amplifier does not have. For example an ideal operational amplifier has zero input offset voltage compared to an real operational amplifier. The integrator circuit of Figure Q5 is constructed using an operational amplifier with finite input offset voltage Vos. For the operational amplifier in Figure Q5, all other parameters are assumed to be ideal.
a)Define three other common limitations of a real operational amplifier compared
to an ideal operational amplifier and briefly explain what they are.(3)
b)What is the value of the current I1 into the positive input of the operational amplifier? Give reasons for your choice of value. (2)
c)What is the voltage across the resistor R1? What is the voltage between the positive and negative input of the operational amplifier? Give reasons for your answers . (3)
d)What is the equation for the current I flowing through the resistor R at the positive input of the operational amplifier in terms of the input voltage Vin and input offset voltage VOS. (2)
e)Derive an equation for the output voltage from this circuit if the input offset voltage is zero. Assume that, initially the capacitor holds no charge and show all mathematical steps. (5)
QUESTION 5 CONTINUED ON PAGE 9/11
f)Prove that the output voltage of the circuit in Figure Q5 with zero input voltage is determined by the size of the input offset voltage and related to the time constant RC by the expression: VOS+ (1/RC)VOSt, in which ‘t’ is the time variable. Show all mathematical steps. (7)
g)If the input offset voltage of the operational amplifier is VOS=1mV and the time constant RC is 10s, what will the rate of change of the output voltage be if the input voltage is zero. Show all mathematical steps. (3)
Integrator Circuit
Figure Q5
6) Figure Q6 shows an inverting amplifier circuit. Assume that the Op Amp has infinite input impedance, a finite input error voltage and that the open loop gain may be approximated by a multi-pole open loop gain bode plot. The open loop bode plot has a ‘flat’ gain of Ap1 dBs from low frequencies to frequency fp1. Above the pole frequency fp1 the open loop gain falls at –20dBs for every decade change in frequency. At the higher pole frequency fp2>fp1 the gain is Ap2 and above this pole frequency the open loop gain of the op amp falls at
–40dBs/decade.
a)Sketch the open loop multi-pole gain magnitude Bode approximation for the Op Amp. Indicate the frequencies fp1 and fp2 with corresponding gains Ap1 and Ap2, together with significant gradients. If the closed loop gain for the circuit in Figure Q6 is ‘–A’, indicate on your sketch the bandwidth at this frequency and label it frequency ‘f’, where by A<Ap2. (6)
b)The inverting amplifier circuit in figure Q6 has an input difference voltage . Give a detailed explanation of what the relationship is between the current I1 in the resistor R1 in terms of the input voltage Vin, difference voltage and resistor value R1? (2)
c)What is the relationship between the current I2 in the feedback resistor R2 and the current I1 in the resistor R1? Explain why they have the relationship you have proposed. (2)
d)Derive an expression for the voltage relationship between the input voltage Vin and output voltage Vout for the inverting amplifier circuit in figure Q6, taking account of the input difference voltage . Show all mathematical steps in your derivation. (6)
e)Develop an equation for the closed loop gain A dBs in terms of the open loop gain Ap1 dBs the frequency ‘f’ and pole frequency fp1, Assume the frequency fp2 is 1000 times higher than the pole frequency fp1. (9)
QUESTION 6 CONTINUED ON PAGE 11/11
Inverting amplifier circuit
Figure Q6